From: Mathieu Desnoyers Date: Sat, 13 Jun 2009 23:18:38 +0000 (-0400) Subject: Other timing tests, update cache line size X-Git-Tag: v0.1~147 X-Git-Url: https://git.lttng.org./?a=commitdiff_plain;h=b430c6d447b85bc1412b0d2b4bdffb3e7573468a;p=userspace-rcu.git Other timing tests, update cache line size Signed-off-by: Mathieu Desnoyers --- diff --git a/test_perthreadlock_timing.c b/test_perthreadlock_timing.c index 625f999..3e8268b 100644 --- a/test_perthreadlock_timing.c +++ b/test_perthreadlock_timing.c @@ -33,6 +33,9 @@ #include #include +/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ +#define CACHE_LINE_SIZE 4096 + #if defined(_syscall0) _syscall0(pid_t, gettid) #elif defined(__NR_gettid) @@ -58,7 +61,7 @@ static struct test_array test_array = { 8 }; struct per_thread_lock { pthread_mutex_t lock; -} __attribute__((aligned(128))); /* cache-line aligned */ +} __attribute__((aligned(CACHE_LINE_SIZE))); /* cache-line aligned */ static struct per_thread_lock *per_thread_lock; @@ -76,8 +79,8 @@ static int num_write; #define NR_READ num_read #define NR_WRITE num_write -static cycles_t __attribute__((aligned(128))) *reader_time; -static cycles_t __attribute__((aligned(128))) *writer_time; +static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *reader_time; +static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *writer_time; void *thr_reader(void *arg) { diff --git a/test_qsbr_timing.c b/test_qsbr_timing.c index e296ced..e46a435 100644 --- a/test_qsbr_timing.c +++ b/test_qsbr_timing.c @@ -32,6 +32,9 @@ #include #include +/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ +#define CACHE_LINE_SIZE 4096 + #if defined(_syscall0) _syscall0(pid_t, gettid) #elif defined(__NR_gettid) @@ -93,8 +96,8 @@ static int num_write; #define NR_READ num_read #define NR_WRITE num_write -static cycles_t __attribute__((aligned(128))) *reader_time; -static cycles_t __attribute__((aligned(128))) *writer_time; +static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *reader_time; +static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *writer_time; void *thr_reader(void *arg) { diff --git a/test_rwlock_timing.c b/test_rwlock_timing.c index cd20876..4884e4d 100644 --- a/test_rwlock_timing.c +++ b/test_rwlock_timing.c @@ -33,6 +33,9 @@ #include #include +/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ +#define CACHE_LINE_SIZE 4096 + #if defined(_syscall0) _syscall0(pid_t, gettid) #elif defined(__NR_gettid) @@ -72,8 +75,8 @@ static int num_write; #define NR_READ num_read #define NR_WRITE num_write -static cycles_t __attribute__((aligned(128))) *reader_time; -static cycles_t __attribute__((aligned(128))) *writer_time; +static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *reader_time; +static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *writer_time; void *thr_reader(void *arg) { diff --git a/test_urcu_timing.c b/test_urcu_timing.c index 5f75bae..8577b8f 100644 --- a/test_urcu_timing.c +++ b/test_urcu_timing.c @@ -32,6 +32,9 @@ #include #include +/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */ +#define CACHE_LINE_SIZE 4096 + #if defined(_syscall0) _syscall0(pid_t, gettid) #elif defined(__NR_gettid) @@ -93,8 +96,8 @@ static int num_write; #define NR_READ num_read #define NR_WRITE num_write -static cycles_t __attribute__((aligned(128))) *reader_time; -static cycles_t __attribute__((aligned(128))) *writer_time; +static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *reader_time; +static cycles_t __attribute__((aligned(CACHE_LINE_SIZE))) *writer_time; void *thr_reader(void *arg) {