From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Date: Sat, 7 Dec 2013 06:00:53 +0000 (+0100)
Subject: x86 barrier for Xeon Phi: use rsp on x86-64
X-Git-Tag: v0.9.0~117
X-Git-Url: https://git.lttng.org./?a=commitdiff_plain;h=b33e85a89e3fab8e58c8932d3d22e802de8d3ab2;p=urcu.git

x86 barrier for Xeon Phi: use rsp on x86-64

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
---

diff --git a/urcu/arch/x86.h b/urcu/arch/x86.h
index 5853604..7af1ca5 100644
--- a/urcu/arch/x86.h
+++ b/urcu/arch/x86.h
@@ -55,9 +55,15 @@ extern "C" {
  * IDT WinChip supports weak store ordering, and the kernel may enable it
  * under our feet; cmm_smp_wmb() ceases to be a nop for these processors.
  */
+#if (CAA_BITS_PER_LONG == 32)
 #define cmm_mb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
-#define cmm_rmb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
-#define cmm_wmb()   __asm__ __volatile__ ("lock; addl $0,0(%%esp)"::: "memory")
+#define cmm_rmb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
+#define cmm_wmb()    __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory")
+#else
+#define cmm_mb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#define cmm_rmb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#define cmm_wmb()    __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory")
+#endif
 #endif
 
 #define caa_cpu_relax()	__asm__ __volatile__ ("rep; nop" : : : "memory");