From: Mathieu Desnoyers Date: Thu, 11 Apr 2024 20:09:26 +0000 (-0400) Subject: ring buffer: Use cpu_dcache_is_aliasing() X-Git-Url: https://git.lttng.org./?a=commitdiff_plain;h=18fd64422b4297f9beea82f1c1a97b80791312e4;p=lttng-modules.git ring buffer: Use cpu_dcache_is_aliasing() Upstream Linux commit 8690bbcf3b7 ("Introduce cpu_dcache_is_aliasing() across all architectures") allows checking whether the architecture has aliasing data caches more accurately. This will be present in upstream Linux v6.9 (currently in v6.9-rc3). I expect this to improve the ring buffer performance on ARM64 and 32-bit ARM with non-aliasing data caches. Signed-off-by: Mathieu Desnoyers Change-Id: I3e29966b8c8cab098d57437a11f1f94c53a9e186 --- diff --git a/src/lib/ringbuffer/ring_buffer_frontend.c b/src/lib/ringbuffer/ring_buffer_frontend.c index 5316b7ff..fbf3a168 100644 --- a/src/lib/ringbuffer/ring_buffer_frontend.c +++ b/src/lib/ringbuffer/ring_buffer_frontend.c @@ -1210,6 +1210,16 @@ static void lib_ring_buffer_flush_read_subbuf_dcache( if (config->output != RING_BUFFER_MMAP) return; +#ifdef cpu_dcache_is_aliasing + /* + * Some architectures implement flush_dcache_page() but don't + * actually have aliasing dcache. cpu_dcache_is_aliasing() was + * introduced in kernel v6.9 to query this more precisely. + */ + if (!cpu_dcache_is_aliasing()) + return; +#endif + /* * Architectures with caches aliased on virtual addresses may * use different cache lines for the linear mapping vs