From: Paolo Bonzini Date: Thu, 22 Sep 2011 09:12:44 +0000 (-0400) Subject: cmm: provide lightweight smp_rmb/smp_wmb on PPC X-Git-Tag: v0.6.5~11 X-Git-Url: https://git.lttng.org./?a=commitdiff_plain;h=0174d10df0bd3a6b1a1e4eb3601476b0536d5dfc;p=urcu.git cmm: provide lightweight smp_rmb/smp_wmb on PPC lwsync orders loads in cacheable memory with respect to other loads, and stores in cacheable memory with respect to other stores. Use it to implement smp_rmb/smp_wmb. The heavy-weight sync is still used for the "full" rmb/wmb operations, as well as for smp_mb. [ Edit by Mathieu Desnoyers: rephrased the comments around the memory barriers. ] Signed-off-by: Paolo Bonzini Signed-off-by: Mathieu Desnoyers --- diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h index a03d688..048b217 100644 --- a/urcu/arch/ppc.h +++ b/urcu/arch/ppc.h @@ -32,7 +32,24 @@ extern "C" { /* Include size of POWER5+ L3 cache lines: 256 bytes */ #define CAA_CACHE_LINE_SIZE 256 -#define cmm_mb() asm volatile("sync":::"memory") +/* + * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not + * preserve ordering of cacheable vs. non-cacheable accesses, so it + * should not be used to order with respect to MMIO operations. An + * eieio+lwsync pair is also not enough for cmm_rmb, because it will + * order cacheable and non-cacheable memory operations separately---i.e. + * not the latter against the former. + */ +#define cmm_mb() asm volatile("sync":::"memory") + +/* + * lwsync orders loads in cacheable memory with respect to other loads, + * and stores in cacheable memory with respect to other stores. + * Therefore, use it for barriers ordering accesses to cacheable memory + * only. + */ +#define cmm_smp_rmb() asm volatile("lwsync":::"memory") +#define cmm_smp_wmb() asm volatile("lwsync":::"memory") #define mftbl() \ ({ \