urcu/uatomic/riscv: Mark RISC-V as broken
authorOlivier Dion <odion@efficios.com>
Thu, 28 Sep 2023 16:53:46 +0000 (12:53 -0400)
committerMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Mon, 2 Oct 2023 15:24:04 +0000 (11:24 -0400)
Implementations of some atomic operations of GCC for RISC-V are
insufficient for sequential consistency. For this reason Userspace RCU
is currently marked as `broken' for RISC-V with GCC. However, it is
still possible to use other toolchains.

See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831 for details.

For now, we mark every version of GCC as unsupported. Distribution
package maintainers will have to cherry-pick the relevant patches in GCC
then remove the #error in Userspace RCU if they want to support it.

As for us, we will incrementally add specific versions of GCC that have
fixed the issue whenever new stable releases are made from the GCC
project.

Change-Id: I2cd7c8f12068628b845a096e03f5f8100eacbe43
Signed-off-by: Olivier Dion <odion@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
include/urcu/uatomic/riscv.h

index a6700e17e2429567fbe1e4e95117bf0c69c7c0f0..66a2b0644c61c65492060f2527392a0498207ab6 100644 (file)
  * IN THE SOFTWARE.
  */
 
+/*
+ * See <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831> for details.
+ *
+ * Until the following patches are backported, Userspace RCU is broken for the
+ * RISC-V architecture when compiled with GCC.
+ *
+ *  - <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4990cf84c460f064d6281d0813f20b0ef20c7448>
+ *  - <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4990cf84c460f064d6281d0813f20b0ef20c7448>
+ *  - <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d199d2e56da2379004e7e0457150409c0c99d3e6>
+ */
+#if defined(__GNUC__)
+#  error "Implementations of some atomic operations of GCC for RISC-V \
+          are insufficient for sequential consistency. For this reason \
+          Userspace RCU is currently marked as 'broken' for RISC-V with \
+          GCC. However, it is still possible to use other toolchains."
+#endif
+
 #ifndef _URCU_ARCH_UATOMIC_RISCV_H
 #define _URCU_ARCH_UATOMIC_RISCV_H
 
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