define CACHE_LINE_SIZE in arch_*.h

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>

diff --git a/tests/api_ppc.h b/tests/api_ppc.h
index da1201936a0a357e484280f0755512aaa4c84d5a..c351d4d18a865a5d393113197ab63f1cc8a198a2 100644 (file)
--- a/tests/api_ppc.h
+++ b/tests/api_ppc.h
@@ -73,7 +73,7 @@
 
 #define CONFIG_PPC64
 
-#define CACHE_LINE_SIZE 128
+/*#define CACHE_LINE_SIZE 128 */
 #define ____cacheline_internodealigned_in_smp \
        __attribute__((__aligned__(1 << 7)))
 
@@ -665,7 +665,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
  */
 
 #ifndef CACHE_LINE_SIZE
-#define CACHE_LINE_SIZE 128
+/* #define CACHE_LINE_SIZE 128 */
 #endif /* #ifndef CACHE_LINE_SIZE */
 
 /*

diff --git a/tests/api_x86.h b/tests/api_x86.h
index 77d86a13a0208b5db189a6c17add55c92e262132..95f4c93d41114e50e2059a87060945ba959490e3 100644 (file)
--- a/tests/api_x86.h
+++ b/tests/api_x86.h
@@ -71,7 +71,7 @@
  * Machine parameters.
  */
 
-#define CACHE_LINE_SIZE 64
+/* #define CACHE_LINE_SIZE 64 */
 #define ____cacheline_internodealigned_in_smp \
        __attribute__((__aligned__(1 << 6)))
 

diff --git a/tests/test_mutex.c b/tests/test_mutex.c
index e3b1b645204f0cbc256b8b0ddfb256217c7c74a4..f2ef706405d159116cac5bead121ea37d3a44bd5 100644 (file)
--- a/tests/test_mutex.c
+++ b/tests/test_mutex.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_perthreadlock.c b/tests/test_perthreadlock.c
index ea47e468f340fec3b9436bd8559dc743c0bcd4a3..8e0800f4b1a48408ae09e54dc0efecdafee88a53 100644 (file)
--- a/tests/test_perthreadlock.c
+++ b/tests/test_perthreadlock.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_perthreadlock_timing.c b/tests/test_perthreadlock_timing.c
index 10720cbfe1f14aaf7f08db75f4d8afaa750ee284..9761f5d9204c9eb0d60f641e1e1a52e7753588f4 100644 (file)
--- a/tests/test_perthreadlock_timing.c
+++ b/tests/test_perthreadlock_timing.c
@@ -34,9 +34,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)

diff --git a/tests/test_qsbr.c b/tests/test_qsbr.c
index cf2fec2a8cbc8ce19f366ce669412bf3842ef5f5..6230510ab39688d9ba8524e6aadc9bc721470883 100644 (file)
--- a/tests/test_qsbr.c
+++ b/tests/test_qsbr.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_qsbr_gc.c b/tests/test_qsbr_gc.c
index d32d1a04175159bc186aeb9f3fbf6f98e98a837a..97660676e548f08d55cc7b3aadf51c066c03338d 100644 (file)
--- a/tests/test_qsbr_gc.c
+++ b/tests/test_qsbr_gc.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_qsbr_timing.c b/tests/test_qsbr_timing.c
index 3585f83470a9ed28120312dd3d4c5fb8e4293b62..bbe983e8da53efba99733c94deb59466157f72b6 100644 (file)
--- a/tests/test_qsbr_timing.c
+++ b/tests/test_qsbr_timing.c
@@ -32,9 +32,6 @@
 #include <sys/syscall.h>
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)

diff --git a/tests/test_rwlock.c b/tests/test_rwlock.c
index d3f072ce14350e2c54b6cdb07c13e42f50ed1e87..923ecad946b050e4c1535efba941aa8d5cdf1b1b 100644 (file)
--- a/tests/test_rwlock.c
+++ b/tests/test_rwlock.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_rwlock_timing.c b/tests/test_rwlock_timing.c
index b26f83dcc9035c20ea878896bc8b1477eaa64a76..c5c947895458d19311f8ff8774f8579cfc521fc7 100644 (file)
--- a/tests/test_rwlock_timing.c
+++ b/tests/test_rwlock_timing.c
@@ -33,9 +33,6 @@
 #include <pthread.h>
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)

diff --git a/tests/test_urcu.c b/tests/test_urcu.c
index 8d090ebdd070ab0fb3e64c010d91675365d48861..3b838c147e2b8ca3ddf866c6218937ac5c8ba2bb 100644 (file)
--- a/tests/test_urcu.c
+++ b/tests/test_urcu.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_urcu_defer.c b/tests/test_urcu_defer.c
index 1c6f742b13aa841b47f203c39fa633ecf3f6db61..08e3e60b404927ae9c76b275f8bf12e5f498dc9a 100644 (file)
--- a/tests/test_urcu_defer.c
+++ b/tests/test_urcu_defer.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_urcu_gc.c b/tests/test_urcu_gc.c
index 60f7816b36fe50fa7d2ecf5a6d12a0ea38b8a8d8..162fae0490e3748decc57d04dd53909b05ad91a2 100644 (file)
--- a/tests/test_urcu_gc.c
+++ b/tests/test_urcu_gc.c
@@ -35,9 +35,6 @@
 
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 /* hardcoded number of CPUs */
 #define NR_CPUS 16384
 

diff --git a/tests/test_urcu_timing.c b/tests/test_urcu_timing.c
index 27d973048a757cd7a86d95fbdcb8b71791220cde..13c0993570817560b4e45809db9660bf0f09b074 100644 (file)
--- a/tests/test_urcu_timing.c
+++ b/tests/test_urcu_timing.c
@@ -32,9 +32,6 @@
 #include <sys/syscall.h>
 #include <urcu/arch.h>
 
-/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
-#define CACHE_LINE_SIZE 4096
-
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)

diff --git a/urcu/arch_ppc.h b/urcu/arch_ppc.h
index 8dfd6d161970432a2225082295a424249af4b980..aaf61d30f03e7749823f0aff154987a07398e071 100644 (file)
--- a/urcu/arch_ppc.h
+++ b/urcu/arch_ppc.h
@@ -28,6 +28,9 @@
 #define CONFIG_HAVE_FENCE 1
 #define CONFIG_HAVE_MEM_COHERENCY
 
+/* Include size of POWER5+ L3 cache lines: 256 bytes */
+#define CACHE_LINE_SIZE        256
+
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG  (__SIZEOF_LONG__ * 8)
 #endif

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index 29612e0a98aa3bfbae4de0ff865259f2418de27d..d455b89b15671fe9a2da8be8dd570907cc01f984 100644 (file)
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -29,6 +29,8 @@
 #define CONFIG_HAVE_FENCE 1
 #define CONFIG_HAVE_MEM_COHERENCY
 
+#define CACHE_LINE_SIZE        128
+
 #ifndef BITS_PER_LONG
 #define BITS_PER_LONG  (__SIZEOF_LONG__ * 8)
 #endif