urcu/arch/generic: Use atomic builtins if configured
authorOlivier Dion <odion@efficios.com>
Wed, 29 Mar 2023 18:43:15 +0000 (14:43 -0400)
committerMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Mon, 14 Aug 2023 19:39:01 +0000 (15:39 -0400)
If configured to use atomic builtins, implement SMP memory barriers in
term of atomic builtins if the architecture does not implement its own
version.

Change-Id: Iddc4283606e0fce572e104d2d3f03b5c0d9926fb
Co-authored-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Olivier Dion <odion@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
include/urcu/arch/generic.h

index c02a6a9930d0b7126c24ac633b5995cfe18e6546..f9e115f14e190c6da199b6d005d9515641b4be56 100644 (file)
@@ -31,6 +31,28 @@ extern "C" {
  * GCC builtins) as well as cmm_rmb and cmm_wmb (defaulting to cmm_mb).
  */
 
+#ifdef CONFIG_RCU_USE_ATOMIC_BUILTINS
+
+# ifndef cmm_smp_mb
+#  define cmm_smp_mb() __atomic_thread_fence(__ATOMIC_SEQ_CST)
+# endif
+
+#endif /* CONFIG_RCU_USE_ATOMIC_BUILTINS */
+
+
+/*
+ * cmm_mb() expands to __sync_synchronize() instead of __atomic_thread_fence
+ * with SEQ_CST because the former "issues a full memory barrier" while the
+ * latter "acts as a synchronization fence between threads" which is too weak
+ * for what we want, for example with I/O devices.
+ *
+ * Even though sync_synchronize seems to be an alias for a sequential consistent
+ * atomic thread fence on every architecture on GCC and Clang, this assumption
+ * might be untrue in future.  Therefore, the definitions above are used to
+ * ensure correct behavior in the future.
+ *
+ * The above defintions are quoted from the GCC manual.
+ */
 #ifndef cmm_mb
 #define cmm_mb()    __sync_synchronize()
 #endif
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