(3) Make LTTV aware of type formats (visual separators) defined in the XML
file.<br>
(3) Use a per architecture enumeration for traps.<br>
+(3) Change the byte pair "facility, event" id for a short combining the
+informatinon.<br>
(4) Statistics per time window.<br>
(4) Disable plugins when threshold reached (i.e. too much process in control
flow view). Draw, and, when the threshold is reached, stop drawing. The global
statistics view can inhibit showing the per process stats.<br>
+(4) Add a visual artifact : PID 0 could be named swapper instead of UNNAMED for
+cpus > 0.<br>
(4) Add event specific fields support to filter.<br>
(4) Add a periodic event interval view. (useful to verify event periodicity)<br>
(4) create a graphical per cpu activity view.<br>
+(4) Add CPU, network, disk, memory usage histogram. [Per interval statistics]<br>
(5) Add Python scripting hooks.<br>
(5) Flight recorder : start lttd automatically upon GUI trace control stop.<br>
(5) Automatically detect traces with too much processes and disable faulty operations.<br>
<big>LTT Next Generation Roadmap<small><br>
<br>
* TODO<br>
+(3) Find a way to make logging know when it causes a minor page fault
+recursively (without ignoring silently all nested events).<br>
+(3) Change the byte pair "facility, event" id for a short combining the
+informatinon.<br>
(4) Add Xen support.<br>
# <A HREF="mailto:Mathieu Desnoyers <compudj@krystal.dyndns.org>">Mathieu Desnoyers</A><br>
# <A HREF="mailto:Parisa Heidari <parisa.heidari@polymtl.ca>">Parisa Heidari</A><br>
(4) efficient dynamic event filtering while recording trace.<br>
% Sensis Corp. <A HREF="mailto:Bish, Tim <Tim.Bish@Sensis.com>">Tim Bish</A><br>
(4) instrument kernel bottom half irqsave, spinlocks, rwlocks, seqlocks, semaphores, mutexes, brlock.<br>
+(4) Try to use my own non LOCK prefixed version of atomic operations : we are
+using per-CPU variables, so it should make it possible.<br>
(4) integrate NPTL instrumentation (see
<A HREF="http://nptltracetool.sourceforge.net/">PTT</A>).<br>
(5) Support CPUs with scalable frequency.<br>