Deal with POWER5+ 256B L3 cachefalse sharing for per thread lock
authorMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Sat, 13 Jun 2009 23:10:31 +0000 (19:10 -0400)
committerMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Sat, 13 Jun 2009 23:10:31 +0000 (19:10 -0400)
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
test_mutex.c
test_perthreadlock.c
test_qsbr.c
test_rwlock.c
test_urcu.c

index d48181082af7ab3a5c5aefd86ff716c96b5337d8..8b480403fcabdd4adccfe0774c51a9d8a45cb42d 100644 (file)
@@ -35,6 +35,9 @@
 
 #include "arch.h"
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)
@@ -104,8 +107,10 @@ static int test_duration_read(void)
 static unsigned long long __thread nr_writes;
 static unsigned long long __thread nr_reads;
 
-static unsigned long long __attribute__((aligned(128))) *tot_nr_writes;
-static unsigned long long __attribute__((aligned(128))) *tot_nr_reads;
+static
+unsigned long long __attribute__((aligned(CACHE_LINE_SIZE))) *tot_nr_writes;
+static
+unsigned long long __attribute__((aligned(CACHE_LINE_SIZE))) *tot_nr_reads;
 
 static unsigned int nr_readers;
 static unsigned int nr_writers;
index 89cce65be71fbdb8badbebedc936b6611e7dc697..3fc4a537f89c98f9556fe706ddb9eb65b85da675 100644 (file)
@@ -35,6 +35,9 @@
 
 #include "arch.h"
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)
@@ -63,7 +66,7 @@ struct test_array {
 
 struct per_thread_lock {
        pthread_mutex_t lock;
-} __attribute__((aligned(128)));       /* cache-line aligned */
+} __attribute__((aligned(CACHE_LINE_SIZE)));   /* cache-line aligned */
 
 static struct per_thread_lock *per_thread_lock;
 
@@ -108,8 +111,10 @@ static int test_duration_read(void)
 static unsigned long long __thread nr_writes;
 static unsigned long long __thread nr_reads;
 
-static unsigned long long __attribute__((aligned(128))) *tot_nr_writes;
-static unsigned long long __attribute__((aligned(128))) *tot_nr_reads;
+static
+unsigned long long __attribute__((aligned(CACHE_LINE_SIZE))) *tot_nr_writes;
+static
+unsigned long long __attribute__((aligned(CACHE_LINE_SIZE))) *tot_nr_reads;
 
 static unsigned int nr_readers;
 static unsigned int nr_writers;
index dc871dc118ee9c82d5fd1676533eef1751552844..2e1a0ecff23f183ed43a920b495b8c1c61bf7dff 100644 (file)
@@ -35,6 +35,9 @@
 
 #include "arch.h"
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)
index 915027db2423df113e7e6a85add6079a257fcb91..733263be628be26b443678eb7d5ec5d687082952 100644 (file)
@@ -35,6 +35,9 @@
 
 #include "arch.h"
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)
index 696c09e39e3b254da74f4ce82766468f0bd03a21..fc9e8b539a9b3a9f21eb05702230602dd760b6d0 100644 (file)
@@ -35,6 +35,9 @@
 
 #include "arch.h"
 
+/* Make this big enough to include the POWER5+ L3 cacheline size of 256B */
+#define CACHE_LINE_SIZE 4096
+
 #if defined(_syscall0)
 _syscall0(pid_t, gettid)
 #elif defined(__NR_gettid)
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