From 2e577577a1e69ecf9ab6634c531c72e1a10c52d9 Mon Sep 17 00:00:00 2001 From: compudj Date: Tue, 8 Apr 2008 05:08:47 +0000 Subject: [PATCH] update git-svn-id: http://ltt.polymtl.ca/svn@2875 04897980-b3bd-0310-b5e0-8ef037075253 --- markers-test/Makefile | 1 - markers-test/test-mark-speed-edit.c | 25 +++++++++++++++++++++++-- markers-test/test-mark-speed-empty.c | 24 ++++++++++++++++++++++-- markers-test/test-mark-speed-local.c | 24 ++++++++++++++++++++++-- markers-test/test-mark-speed-opt.c | 24 ++++++++++++++++++++++-- markers-test/test-mark-speed.c | 23 +++++++++++++++++++++-- 6 files changed, 110 insertions(+), 11 deletions(-) diff --git a/markers-test/Makefile b/markers-test/Makefile index d07a8292..4499bb27 100644 --- a/markers-test/Makefile +++ b/markers-test/Makefile @@ -4,7 +4,6 @@ ifneq ($(KERNELRELEASE),) obj-m += test-mark-speed-edit.o obj-m += test-mark-speed-opt.o obj-m += test-mark-speed-local.o - obj-m += cachectl.o else KERNELDIR ?= /lib/modules/$(shell uname -r)/build PWD := $(shell pwd) diff --git a/markers-test/test-mark-speed-edit.c b/markers-test/test-mark-speed-edit.c index 5e104563..ebae25d2 100644 --- a/markers-test/test-mark-speed-edit.c +++ b/markers-test/test-mark-speed-edit.c @@ -10,6 +10,27 @@ #include #include +static void pmc_flush_cache(void) + { + /* write back and invalidate cache (a serializing instruction) */ + + __asm__ __volatile__ ( "wbinvd" : : : "memory" ); + + /* The wbinvd instruction does not wait for the external caches + * to be flushed, but only requests that it be done. The loop + * is to be sure that enough time has elapsed, but the compiler + * might simplify or even remove it. The loop bound is for a + * 512 KB L2 cache. On a Pentium Pro/II/III, the loop uses + * 2 cycles per iteration. + * + * Does wbinvd also cause the TLB to be flushed? + * A comment in mtrr.c suggests that it does. + */ + { register int i; for (i = 0; i < 512*1024; i++) { } } + } + + + static void noinline test2(const struct marker *mdata, void *call_private, ...) { @@ -69,7 +90,7 @@ char temp5[8192]; static inline void test(unsigned long arg, unsigned long arg2) { #ifdef CACHEFLUSH - wbinvd(); + pmc_flush_cache(); #endif temp[2] = (temp[0] + 60) << 10; temp[3] = (temp[2] + 60) << 10; @@ -91,7 +112,7 @@ static int my_open(struct inode *inode, struct file *file) local_irq_save(flags); #ifdef CACHEFLUSH - wbinvd(); /* initial write back, without cycle count */ + pmc_flush_cache(); /* initial write back, without cycle count */ msleep(20); /* wait for L2 flush */ #endif rdtsc_barrier(); diff --git a/markers-test/test-mark-speed-empty.c b/markers-test/test-mark-speed-empty.c index ceaac9da..a247cacb 100644 --- a/markers-test/test-mark-speed-empty.c +++ b/markers-test/test-mark-speed-empty.c @@ -10,6 +10,26 @@ #include #include +static void pmc_flush_cache(void) + { + /* write back and invalidate cache (a serializing instruction) */ + + __asm__ __volatile__ ( "wbinvd" : : : "memory" ); + + /* The wbinvd instruction does not wait for the external caches + * to be flushed, but only requests that it be done. The loop + * is to be sure that enough time has elapsed, but the compiler + * might simplify or even remove it. The loop bound is for a + * 512 KB L2 cache. On a Pentium Pro/II/III, the loop uses + * 2 cycles per iteration. + * + * Does wbinvd also cause the TLB to be flushed? + * A comment in mtrr.c suggests that it does. + */ + { register int i; for (i = 0; i < 512*1024; i++) { } } + } + + static void noinline test2(const struct marker *mdata, void *call_private, ...) { @@ -59,7 +79,7 @@ char temp5[8192]; static inline void test(unsigned long arg, unsigned long arg2) { #ifdef CACHEFLUSH - wbinvd(); + pmc_flush_cache(); #endif temp[2] = (temp[0] + 60) << 10; temp[3] = (temp[2] + 60) << 10; @@ -80,7 +100,7 @@ static int my_open(struct inode *inode, struct file *file) local_irq_save(flags); #ifdef CACHEFLUSH - wbinvd(); /* initial write back, without cycle count */ + pmc_flush_cache(); /* initial write back, without cycle count */ msleep(20); /* wait for L2 flush */ #endif rdtsc_barrier(); diff --git a/markers-test/test-mark-speed-local.c b/markers-test/test-mark-speed-local.c index 5bcbccb7..552afcea 100644 --- a/markers-test/test-mark-speed-local.c +++ b/markers-test/test-mark-speed-local.c @@ -10,6 +10,26 @@ #include #include +static void pmc_flush_cache(void) + { + /* write back and invalidate cache (a serializing instruction) */ + + __asm__ __volatile__ ( "wbinvd" : : : "memory" ); + + /* The wbinvd instruction does not wait for the external caches + * to be flushed, but only requests that it be done. The loop + * is to be sure that enough time has elapsed, but the compiler + * might simplify or even remove it. The loop bound is for a + * 512 KB L2 cache. On a Pentium Pro/II/III, the loop uses + * 2 cycles per iteration. + * + * Does wbinvd also cause the TLB to be flushed? + * A comment in mtrr.c suggests that it does. + */ + { register int i; for (i = 0; i < 512*1024; i++) { } } + } + + static void noinline test2(const struct marker *mdata, void *call_private, ...) { @@ -68,7 +88,7 @@ char temp5[8192]; static inline void test(unsigned long arg, unsigned long arg2) { #ifdef CACHEFLUSH - wbinvd(); + pmc_flush_cache(); #endif temp[2] = (temp[0] + 60) << 10; temp[3] = (temp[2] + 60) << 10; @@ -90,7 +110,7 @@ static int my_open(struct inode *inode, struct file *file) local_irq_save(flags); #ifdef CACHEFLUSH - wbinvd(); /* initial write back, without cycle count */ + pmc_flush_cache(); /* initial write back, without cycle count */ msleep(20); /* wait for L2 flush */ #endif rdtsc_barrier(); diff --git a/markers-test/test-mark-speed-opt.c b/markers-test/test-mark-speed-opt.c index aa7c2ca6..231285d1 100644 --- a/markers-test/test-mark-speed-opt.c +++ b/markers-test/test-mark-speed-opt.c @@ -10,6 +10,26 @@ #include #include +static void pmc_flush_cache(void) + { + /* write back and invalidate cache (a serializing instruction) */ + + __asm__ __volatile__ ( "wbinvd" : : : "memory" ); + + /* The wbinvd instruction does not wait for the external caches + * to be flushed, but only requests that it be done. The loop + * is to be sure that enough time has elapsed, but the compiler + * might simplify or even remove it. The loop bound is for a + * 512 KB L2 cache. On a Pentium Pro/II/III, the loop uses + * 2 cycles per iteration. + * + * Does wbinvd also cause the TLB to be flushed? + * A comment in mtrr.c suggests that it does. + */ + { register int i; for (i = 0; i < 512*1024; i++) { } } + } + + static void noinline test2(const struct marker *mdata, void *call_private, ...) { @@ -58,7 +78,7 @@ char temp5[8192]; static inline void test(unsigned long arg, unsigned long arg2) { #ifdef CACHEFLUSH - wbinvd(); + pmc_flush_cache(); #endif temp[2] = (temp[0] + 60) << 10; temp[3] = (temp[2] + 60) << 10; @@ -79,7 +99,7 @@ static int my_open(struct inode *inode, struct file *file) local_irq_save(flags); #ifdef CACHEFLUSH - wbinvd(); /* initial write back, without cycle count */ + pmc_flush_cache(); /* initial write back, without cycle count */ msleep(20); /* wait for L2 flush */ #endif rdtsc_barrier(); diff --git a/markers-test/test-mark-speed.c b/markers-test/test-mark-speed.c index 25f45a1a..bd798b8e 100644 --- a/markers-test/test-mark-speed.c +++ b/markers-test/test-mark-speed.c @@ -10,6 +10,25 @@ #include #include +static void pmc_flush_cache(void) + { + /* write back and invalidate cache (a serializing instruction) */ + + __asm__ __volatile__ ( "wbinvd" : : : "memory" ); + + /* The wbinvd instruction does not wait for the external caches + * to be flushed, but only requests that it be done. The loop + * is to be sure that enough time has elapsed, but the compiler + * might simplify or even remove it. The loop bound is for a + * 512 KB L2 cache. On a Pentium Pro/II/III, the loop uses + * 2 cycles per iteration. + * + * Does wbinvd also cause the TLB to be flushed? + * A comment in mtrr.c suggests that it does. + */ + { register int i; for (i = 0; i < 512*1024; i++) { } } + } + static void noinline test2(const struct marker *mdata, void *call_private, ...) { @@ -59,7 +78,7 @@ char temp5[8192]; static inline void test(unsigned long arg, unsigned long arg2) { #ifdef CACHEFLUSH - wbinvd(); + pmc_flush_cache(); #endif temp[2] = (temp[0] + 60) << 10; temp[3] = (temp[2] + 60) << 10; @@ -80,7 +99,7 @@ static int my_open(struct inode *inode, struct file *file) local_irq_save(flags); #ifdef CACHEFLUSH - wbinvd(); /* initial write back, without cycle count */ + pmc_flush_cache(); /* initial write back, without cycle count */ msleep(20); /* wait for L2 flush */ #endif rdtsc_barrier(); -- 2.34.1