From 1993e033c4af6ac822f510c29e468de0725012d8 Mon Sep 17 00:00:00 2001
From: compudj <compudj@04897980-b3bd-0310-b5e0-8ef037075253>
Date: Tue, 8 Apr 2008 05:25:54 +0000
Subject: [PATCH] update

git-svn-id: http://ltt.polymtl.ca/svn@2878 04897980-b3bd-0310-b5e0-8ef037075253
---
 markers-test/test-mark-speed-edit.c  |  8 ++++++--
 markers-test/test-mark-speed-empty.c |  7 +++++--
 markers-test/test-mark-speed-local.c |  7 +++++--
 markers-test/test-mark-speed-opt.c   |  7 +++++--
 markers-test/test-mark-speed.c       | 11 +++++++----
 5 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/markers-test/test-mark-speed-edit.c b/markers-test/test-mark-speed-edit.c
index 2aeab6e2..3c8964f1 100644
--- a/markers-test/test-mark-speed-edit.c
+++ b/markers-test/test-mark-speed-edit.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,10 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    
+     for (i = 0; i < 512*1024; i++) {
+       cpu_relax();
+     }
   }
 
 
@@ -85,7 +89,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-	register int temp[5];
+	volatile int temp[5];
 #ifdef CACHEFLUSH
 	pmc_flush_cache();
 #endif
diff --git a/markers-test/test-mark-speed-empty.c b/markers-test/test-mark-speed-empty.c
index caaf907e..edae0550 100644
--- a/markers-test/test-mark-speed-empty.c
+++ b/markers-test/test-mark-speed-empty.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,9 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
   }
 
 
@@ -74,7 +77,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-	register int temp[5];
+	volatile int temp[5];
 #ifdef CACHEFLUSH
 	pmc_flush_cache();
 #endif
diff --git a/markers-test/test-mark-speed-local.c b/markers-test/test-mark-speed-local.c
index e0bb5fd4..63d8f9dc 100644
--- a/markers-test/test-mark-speed-local.c
+++ b/markers-test/test-mark-speed-local.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,9 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
   }
 
 
@@ -83,7 +86,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-	register int temp[5];
+	volatile int temp[5];
 #ifdef CACHEFLUSH
 	pmc_flush_cache();
 #endif
diff --git a/markers-test/test-mark-speed-opt.c b/markers-test/test-mark-speed-opt.c
index d1f716b9..755a41a9 100644
--- a/markers-test/test-mark-speed-opt.c
+++ b/markers-test/test-mark-speed-opt.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,9 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
   }
 
 
@@ -73,7 +76,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-	register int temp[5];
+	volatile int temp[5];
 #ifdef CACHEFLUSH
 	pmc_flush_cache();
 #endif
diff --git a/markers-test/test-mark-speed.c b/markers-test/test-mark-speed.c
index 6658e645..c000df08 100644
--- a/markers-test/test-mark-speed.c
+++ b/markers-test/test-mark-speed.c
@@ -11,7 +11,8 @@
 #include <asm/system.h>
 
 static void pmc_flush_cache(void)
-  {
+{
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,8 +27,10 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
-  }
+    for (i = 0; i < 512*1024; i++) {
+    	cpu_relax();
+    }
+}
 
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
@@ -73,7 +76,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-	register int temp[5];
+	volatile int temp[5];
 #ifdef CACHEFLUSH
 	pmc_flush_cache();
 #endif
-- 
2.34.1