X-Git-Url: http://git.lttng.org./?a=blobdiff_plain;f=markers-test%2Ftest-mark-speed-opt.c;h=bc606a10ad3c1685ad977663639a1c19735f6f1a;hb=fade4071bfc7dcaebaad3e7f502c62a152f659a9;hp=d1f716b96f8e50d333386dbeb433c98aac31de09;hpb=7edac299ab5e10be465174cacac0adb59ebaaa5e;p=lttv.git

diff --git a/markers-test/test-mark-speed-opt.c b/markers-test/test-mark-speed-opt.c
index d1f716b9..bc606a10 100644
--- a/markers-test/test-mark-speed-opt.c
+++ b/markers-test/test-mark-speed-opt.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,9 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
   }
 
 
@@ -73,9 +76,10 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-	register int temp[5];
+	volatile int temp[5];
 #ifdef CACHEFLUSH
-	pmc_flush_cache();
+	clflush(&current->pid);
+	//pmc_flush_cache();
 #endif
 	temp[2] = (temp[0] + 60) << 10;
 	temp[3] = (temp[2] + 60) << 10;
@@ -96,8 +100,8 @@ static int my_open(struct inode *inode, struct file *file)
 
 	local_irq_save(flags);
 #ifdef CACHEFLUSH
-	pmc_flush_cache();	/* initial write back, without cycle count */
-	msleep(20);	/* wait for L2 flush */
+	//pmc_flush_cache();	/* initial write back, without cycle count */
+	//msleep(20);	/* wait for L2 flush */
 #endif
 	rdtsc_barrier();
 	cycles1 = get_cycles();