X-Git-Url: http://git.lttng.org./?a=blobdiff_plain;f=markers-test%2Ftest-mark-speed-empty.c;h=e9ea607b85e09cde3c38517d3752e59a2e404d5a;hb=58310ebf4ad6a55b26cfc10950208f7d83c584f2;hp=296ba88cef482925d94f9a23452fa218810981b7;hpb=f36297ebe40a72dfbd178fba9a796a57793ea6f8;p=lttv.git diff --git a/markers-test/test-mark-speed-empty.c b/markers-test/test-mark-speed-empty.c index 296ba88c..e9ea607b 100644 --- a/markers-test/test-mark-speed-empty.c +++ b/markers-test/test-mark-speed-empty.c @@ -10,6 +10,29 @@ #include #include +static void pmc_flush_cache(void) + { + register int i; + /* write back and invalidate cache (a serializing instruction) */ + + __asm__ __volatile__ ( "wbinvd" : : : "memory" ); + + /* The wbinvd instruction does not wait for the external caches + * to be flushed, but only requests that it be done. The loop + * is to be sure that enough time has elapsed, but the compiler + * might simplify or even remove it. The loop bound is for a + * 512 KB L2 cache. On a Pentium Pro/II/III, the loop uses + * 2 cycles per iteration. + * + * Does wbinvd also cause the TLB to be flushed? + * A comment in mtrr.c suggests that it does. + */ + for (i = 0; i < 512*1024; i++) { + cpu_relax(); + } + } + + static void noinline test2(const struct marker *mdata, void *call_private, ...) { @@ -52,16 +75,17 @@ static void noinline test2(const struct marker *mdata, //asm volatile (""); struct proc_dir_entry *pentry = NULL; -char temp0[8192]; -int temp __cacheline_aligned = 10; -char temp2[8192]; - static inline void test(unsigned long arg, unsigned long arg2) { + volatile int temp[5]; #ifdef CACHEFLUSH - wbinvd(); + clflush(¤t->pid); + //pmc_flush_cache(); #endif - temp = (temp + 60) << 10; + temp[2] = (temp[0] + 60) << 10; + temp[3] = (temp[2] + 60) << 10; + temp[4] = (temp[3] + 60) << 10; + temp[0] = (temp[4] + 60) << 10; barrier(); asm (""); barrier(); @@ -76,6 +100,10 @@ static int my_open(struct inode *inode, struct file *file) unsigned long flags; local_irq_save(flags); +#ifdef CACHEFLUSH + //pmc_flush_cache(); /* initial write back, without cycle count */ + //msleep(20); /* wait for L2 flush */ +#endif rdtsc_barrier(); cycles1 = get_cycles(); rdtsc_barrier();