X-Git-Url: http://git.lttng.org./?a=blobdiff_plain;f=markers-test%2Ftest-mark-speed-empty.c;h=e9ea607b85e09cde3c38517d3752e59a2e404d5a;hb=58310ebf4ad6a55b26cfc10950208f7d83c584f2;hp=10b3ffce8eccf67c2f510944faa8b56bd01420ba;hpb=d39261406fe9d831096ea89f985f95d665b608a3;p=lttv.git

diff --git a/markers-test/test-mark-speed-empty.c b/markers-test/test-mark-speed-empty.c
index 10b3ffce..e9ea607b 100644
--- a/markers-test/test-mark-speed-empty.c
+++ b/markers-test/test-mark-speed-empty.c
@@ -10,6 +10,29 @@
 #include <asm/ptrace.h>
 #include <asm/system.h>
 
+static void pmc_flush_cache(void)
+  {
+    register int i;
+    /* write back and invalidate cache (a serializing instruction) */
+
+    __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+    /* The wbinvd instruction does not wait for the external caches
+     * to be flushed, but only requests that it be done.  The loop
+     * is to be sure that enough time has elapsed, but the compiler
+     * might simplify or even remove it.  The loop bound is for a
+     * 512 KB L2 cache.  On a Pentium Pro/II/III, the loop uses
+     * 2 cycles per iteration.
+     *
+     * Does wbinvd also cause the TLB to be flushed?
+     * A comment in mtrr.c suggests that it does.
+     */
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
+  }
+
+
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
 {
@@ -52,14 +75,12 @@ static void noinline test2(const struct marker *mdata,
 	//asm volatile ("");
 struct proc_dir_entry *pentry = NULL;
 
-char temp0[8192];
-int temp[8192];
-char temp5[8192];
-
 static inline void test(unsigned long arg, unsigned long arg2)
 {
+	volatile int temp[5];
 #ifdef CACHEFLUSH
-	wbinvd();
+	clflush(&current->pid);
+	//pmc_flush_cache();
 #endif
 	temp[2] = (temp[0] + 60) << 10;
 	temp[3] = (temp[2] + 60) << 10;
@@ -80,7 +101,8 @@ static int my_open(struct inode *inode, struct file *file)
 
 	local_irq_save(flags);
 #ifdef CACHEFLUSH
-	wbinvd();	/* initial write back, without cycle count */
+	//pmc_flush_cache();	/* initial write back, without cycle count */
+	//msleep(20);	/* wait for L2 flush */
 #endif
 	rdtsc_barrier();
 	cycles1 = get_cycles();