X-Git-Url: http://git.lttng.org./?a=blobdiff_plain;f=ltt%2Fbranches%2Fpoly%2Fdoc%2Fdeveloper%2Flttng-synthetic-tsc-msb.txt;h=ffac4289ca8c12cfe171c9a3a46ca078c158a99c;hb=1e3e9a0a326d402ea552d73e6d3ff15eb228f884;hp=f59d7c737fe19bf402a618877b93668d03c6ead8;hpb=11904fb650a9421508a4cd1140491423fab5dc34;p=lttv.git

diff --git a/ltt/branches/poly/doc/developer/lttng-synthetic-tsc-msb.txt b/ltt/branches/poly/doc/developer/lttng-synthetic-tsc-msb.txt
index f59d7c73..ffac4289 100644
--- a/ltt/branches/poly/doc/developer/lttng-synthetic-tsc-msb.txt
+++ b/ltt/branches/poly/doc/developer/lttng-synthetic-tsc-msb.txt
@@ -48,4 +48,5 @@ An array of two 64 bits elements. Elements are updated in two memory writes, but
 the element switch (current element) is made atomically. As there is only one
 writer, this has no locking problem.
 
-
+We make sure the synthetic tcs reader does not sleep by disabling preemption. We
+do the same for the writer.