X-Git-Url: http://git.lttng.org./?a=blobdiff_plain;f=ltt%2Fbranches%2Fpoly%2Fdoc%2Fdeveloper%2Flttng-lttv-compatibility.html;h=95c30e85db5b7b1f970176bd778bbd7dd1b7520b;hb=e51383f9018ea2f05b73a76503c44fd5ba1a7e9b;hp=87484f5c0c0defb106267f1420409e03b35af085;hpb=ddf17e9f842c725ed24e9043743429e912472dae;p=lttv.git

diff --git a/ltt/branches/poly/doc/developer/lttng-lttv-compatibility.html b/ltt/branches/poly/doc/developer/lttng-lttv-compatibility.html
index 87484f5c..95c30e85 100644
--- a/ltt/branches/poly/doc/developer/lttng-lttv-compatibility.html
+++ b/ltt/branches/poly/doc/developer/lttng-lttv-compatibility.html
@@ -28,7 +28,7 @@ cellspacing="2" rules="all" frame="border">
 </th>
 <th style="vertical-align: top;">Comments<br>
 </th>
-<th style="vertical-align: top;">Regression ok<br>
+<th style="vertical-align: top;">Kernel Regression ok<br>
 </th>
 <th style="vertical-align: top;">Regression fails/not tested<br>
 </th>
@@ -54,7 +54,7 @@ cellspacing="2" rules="all" frame="border">
 </th>
 <th style="vertical-align: top;">Comments<br>
 </th>
-<th style="vertical-align: top;">Regression ok<br>
+<th style="vertical-align: top;">Kernel Regression ok<br>
 </th>
 <th style="vertical-align: top;">Regression fails/not tested<br>
 </th>
@@ -85,6 +85,10 @@ cellspacing="2" rules="all" frame="border">
 </td>
 <td style="vertical-align: top;"><br>
 </td>
+<td style="vertical-align: top;"><br>
+</td>
+<td style="vertical-align: top;"><br>
+</td>
 </tr>
 <tr>
 <td style="vertical-align: top;">0.7.0<br>
@@ -2182,9 +2186,11 @@ xtensa.<br>
 <tr>
 <td style="vertical-align: top;">
 0.8.80<br>
+0.8.81<br>
 </td>
 <td style="vertical-align: top;">
 0.6.78<br>
+0.6.80<br>
 </td>
 <td style="vertical-align: top;">
 0.36<br>
@@ -2210,6 +2216,10 @@ Add compact channel.<br>
 Fix start of trace get full timestamp. Caused problems with time gap between
 trace create/start and 32 bits (or less) TSC in events.<br>
 Ok for xen-unstable changeset starting at 14391.<br>
+Adds TSC testing in kernel.<br>
+Adds monotonic logical clock based on highest TSC count for x86 and x86_64 with
+async TSCs.<br>
+Fix missing compat_fs_exec event : rename to fs_exec.<br>
 </td>
 <td style="vertical-align: top;">
 </td>
@@ -2221,6 +2231,99 @@ xtensa.<br>
 
 </tr>
 
+<tr>
+<td style="vertical-align: top;">
+0.8.82<br>
+</td>
+<td style="vertical-align: top;">
+0.9.0<br>
+</td>
+<td style="vertical-align: top;">
+0.37<br>
+</td>
+<td style="vertical-align: top;">
+obsolete<br>
+</td>
+<td style="vertical-align: top;">
+0.29<br>
+</td>
+<td style="vertical-align: top;">
+0.34<br>
+</td>
+<td style="vertical-align: top;">
+0.8<br>
+</td>
+<td style="vertical-align: top;">
+2.6.20<br>
+ARM, MIPS32/64, powerpc32, powerpc64, ppc, i386, x86_64<br>
+</td>
+<td style="vertical-align: top;">
+Introduces the LTT serialization library. Cuts the kernel patch size from
+2M to 500k. Deprecates genevent for kernel instrumentation, but keeps backward
+compatibility with genevent generated code (still used for user space tracing).
+Slightly longer execution time at instrumentation site (270ns vs 200ns for 4
+bytes write on P4 3GHz), but the global advantage of using less memory, and
+therefore less cache, should overweight this cost in cycles. Note : In this
+version, the ltt-probe-* kernel modules and the XML definitions must be kept in
+sync by hand, otherwise, LTTV will detect a size mismatch between the kernel
+trace and the expected event size..<br>
+</td>
+<td style="vertical-align: top;">
+arm, i686, ia64, m68k, mips, mipsel, x86_64, powerpc 405, powerpc64, s390,
+sparc, sparc64.<br>
+</td>
+<td style="vertical-align: top;">
+alpha, arm26, avr32, cris, frv, h8300, m32r, m68knommu, parisc, sh, sh64, um,
+v850, xtensa.<br>
+</td>
+
+</tr>
+
+<tr>
+<td style="vertical-align: top;">
+0.8.82<br>
+</td>
+<td style="vertical-align: top;">
+0.9.1<br>
+0.9.2<br>
+</td>
+<td style="vertical-align: top;">
+0.38<br>
+0.39<br>
+</td>
+<td style="vertical-align: top;">
+obsolete<br>
+</td>
+<td style="vertical-align: top;">
+0.30<br>
+0.31<br>
+</td>
+<td style="vertical-align: top;">
+0.34<br>
+</td>
+<td style="vertical-align: top;">
+0.8<br>
+</td>
+<td style="vertical-align: top;">
+2.6.21-rc6-mm1<br>
+ARM, MIPS32/64, powerpc32, powerpc64, ppc, i386, x86_64<br>
+</td>
+<td style="vertical-align: top;">
+Ported to Andrew Morton's tree.<br>
+</td>
+<td style="vertical-align: top;">
+</td>
+<td style="vertical-align: top;">
+alpha, arm26, avr32, cris, frv, h8300, m32r, m68knommu, parisc, sh, sh64, um,
+v850, xtensa.<br>
+arm, i686, ia64, m68k, mips, mipsel, x86_64, powerpc 405, powerpc64, s390,
+sparc, sparc64.<br>
+</td>
+
+</tr>
+
+
+
 </tbody>
 </table>