update

[lttv.git] / markers-test / test-mark-speed.c

diff --git a/markers-test/test-mark-speed.c b/markers-test/test-mark-speed.c
index bd798b8e3de39eda060cec129b48f0ff69aaa9aa..c000df081e4d26c3412ebe2d8eddbf4fc1fe981e 100644 (file)
--- a/markers-test/test-mark-speed.c
+++ b/markers-test/test-mark-speed.c
@@ -11,7 +11,8 @@
 #include <asm/system.h>
 
 static void pmc_flush_cache(void)
-  {
+{
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,8 +27,10 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
-  }
+    for (i = 0; i < 512*1024; i++) {
+       cpu_relax();
+    }
+}
 
 static void noinline test2(const struct marker *mdata,
         void *call_private, ...)
@@ -71,12 +74,9 @@ static void noinline test2(const struct marker *mdata,
        //asm volatile ("");
 struct proc_dir_entry *pentry = NULL;
 
-char temp0[8192];
-int temp[8192] __cacheline_aligned;
-char temp5[8192];
-
 static inline void test(unsigned long arg, unsigned long arg2)
 {
+       volatile int temp[5];
 #ifdef CACHEFLUSH
        pmc_flush_cache();
 #endif