printk("blah\n");
}
+#ifdef CACHEFLUSH
+#define myclflush(a) clflush(a)
+#else
+#define myclflush(a)
+#endif \
+
/*
* Generic marker flavor always available.
* Note : the empty asm volatile with read constraint is used here instead of a
(&__mark_##name, call_private, \
## args); \
} else { \
+ myclflush(&_imv_read(__mark_##name.state)); \
if (unlikely(_imv_read(__mark_##name.state))) \
test2 \
(&__mark_##name, call_private, \
static inline void test(unsigned long arg, unsigned long arg2)
{
volatile int temp[5];
-#ifdef CACHEFLUSH
- pmc_flush_cache();
-#endif
temp[2] = (temp[0] + 60) << 10;
temp[3] = (temp[2] + 60) << 10;
temp[4] = (temp[3] + 60) << 10;
local_irq_save(flags);
#ifdef CACHEFLUSH
- pmc_flush_cache(); /* initial write back, without cycle count */
- msleep(20); /* wait for L2 flush */
+ //pmc_flush_cache(); /* initial write back, without cycle count */
+ //msleep(20); /* wait for L2 flush */
#endif
rdtsc_barrier();
cycles1 = get_cycles();