static void pmc_flush_cache(void)
{
+ register int i;
/* write back and invalidate cache (a serializing instruction) */
__asm__ __volatile__ ( "wbinvd" : : : "memory" );
* Does wbinvd also cause the TLB to be flushed?
* A comment in mtrr.c suggests that it does.
*/
- { register int i; for (i = 0; i < 512*1024; i++) { } }
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
}
static inline void test(unsigned long arg, unsigned long arg2)
{
- register int temp[5];
+ volatile int temp[5];
#ifdef CACHEFLUSH
- pmc_flush_cache();
+ clflush(¤t->pid);
+ //pmc_flush_cache();
#endif
temp[2] = (temp[0] + 60) << 10;
temp[3] = (temp[2] + 60) << 10;
local_irq_save(flags);
#ifdef CACHEFLUSH
- pmc_flush_cache(); /* initial write back, without cycle count */
- msleep(20); /* wait for L2 flush */
+ //pmc_flush_cache(); /* initial write back, without cycle count */
+ //msleep(20); /* wait for L2 flush */
#endif
rdtsc_barrier();
cycles1 = get_cycles();