{
volatile int temp[5];
#ifdef CACHEFLUSH
- pmc_flush_cache();
+ clflush(¤t->pid);
+ //pmc_flush_cache();
#endif
temp[2] = (temp[0] + 60) << 10;
temp[3] = (temp[2] + 60) << 10;
local_irq_save(flags);
#ifdef CACHEFLUSH
- pmc_flush_cache(); /* initial write back, without cycle count */
- msleep(20); /* wait for L2 flush */
+ //pmc_flush_cache(); /* initial write back, without cycle count */
+ //msleep(20); /* wait for L2 flush */
#endif
rdtsc_barrier();
cycles1 = get_cycles();