update

[lttv.git] / markers-test / test-mark-speed-opt.c

diff --git a/markers-test/test-mark-speed-opt.c b/markers-test/test-mark-speed-opt.c
index d1f716b96f8e50d333386dbeb433c98aac31de09..755a41a94812c049c85270943d1d41d3f99b84ea 100644 (file)
--- a/markers-test/test-mark-speed-opt.c
+++ b/markers-test/test-mark-speed-opt.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,9 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    for (i = 0; i < 512*1024; i++) {
+      cpu_relax();
+    }
   }
 
 
@@ -73,7 +76,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-       register int temp[5];
+       volatile int temp[5];
 #ifdef CACHEFLUSH
        pmc_flush_cache();
 #endif