update

[lttv.git] / markers-test / test-mark-speed-edit.c

diff --git a/markers-test/test-mark-speed-edit.c b/markers-test/test-mark-speed-edit.c
index f3a99837891a0aff968c53cae78c51b17e5b7610..3c8964f17fd1b4746fdb86bc5bbf16133c48ac35 100644 (file)
--- a/markers-test/test-mark-speed-edit.c
+++ b/markers-test/test-mark-speed-edit.c
@@ -12,6 +12,7 @@
 
 static void pmc_flush_cache(void)
   {
+    register int i;
     /* write back and invalidate cache (a serializing instruction) */
 
     __asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@ -26,7 +27,10 @@ static void pmc_flush_cache(void)
      * Does wbinvd also cause the TLB to be flushed?
      * A comment in mtrr.c suggests that it does.
      */
-    { register int i; for (i = 0; i < 512*1024; i++) { } }
+    
+     for (i = 0; i < 512*1024; i++) {
+       cpu_relax();
+     }
   }
 
 
@@ -85,7 +89,7 @@ struct proc_dir_entry *pentry = NULL;
 
 static inline void test(unsigned long arg, unsigned long arg2)
 {
-       int temp[5];
+       volatile int temp[5];
 #ifdef CACHEFLUSH
        pmc_flush_cache();
 #endif