#include <asm/atomic.h>
#include <asm/hw_irq.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
/*
* Memory barrier.
* The sync instruction guarantees that all memory accesses initiated
#define smp_read_barrier_depends() do { } while(0)
#endif /* CONFIG_SMP */
-static __inline__ unsigned long
+static inline unsigned long
xchg_u32(volatile void *p, unsigned long val)
{
unsigned long prev;
#define __HAVE_ARCH_CMPXCHG 1
-static __inline__ unsigned long
+static inline unsigned long
__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
{
unsigned int prev;
if something tries to do an invalid cmpxchg(). */
extern void __cmpxchg_called_with_bad_pointer(void);
-static __inline__ unsigned long
+static inline unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
{
switch (size) {
#define arch_align_stack(x) (x)
+#ifdef __cplusplus
+} /* end of extern "C" */
+#endif
+
#endif /* __PPC_SYSTEM_H */