+static void pmc_flush_cache(void)
+ {
+ register int i;
+ /* write back and invalidate cache (a serializing instruction) */
+
+ __asm__ __volatile__ ( "wbinvd" : : : "memory" );
+
+ /* The wbinvd instruction does not wait for the external caches
+ * to be flushed, but only requests that it be done. The loop
+ * is to be sure that enough time has elapsed, but the compiler
+ * might simplify or even remove it. The loop bound is for a
+ * 512 KB L2 cache. On a Pentium Pro/II/III, the loop uses
+ * 2 cycles per iteration.
+ *
+ * Does wbinvd also cause the TLB to be flushed?
+ * A comment in mtrr.c suggests that it does.
+ */
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
+ }
+
+