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update version
[lttv.git]
/
markers-test
/
test-mark-speed-empty.c
diff --git
a/markers-test/test-mark-speed-empty.c
b/markers-test/test-mark-speed-empty.c
index caaf907e889405f167688e709150deca8d6a7bdb..e9ea607b85e09cde3c38517d3752e59a2e404d5a 100644
(file)
--- a/
markers-test/test-mark-speed-empty.c
+++ b/
markers-test/test-mark-speed-empty.c
@@
-12,6
+12,7
@@
static void pmc_flush_cache(void)
{
static void pmc_flush_cache(void)
{
+ register int i;
/* write back and invalidate cache (a serializing instruction) */
__asm__ __volatile__ ( "wbinvd" : : : "memory" );
/* write back and invalidate cache (a serializing instruction) */
__asm__ __volatile__ ( "wbinvd" : : : "memory" );
@@
-26,7
+27,9
@@
static void pmc_flush_cache(void)
* Does wbinvd also cause the TLB to be flushed?
* A comment in mtrr.c suggests that it does.
*/
* Does wbinvd also cause the TLB to be flushed?
* A comment in mtrr.c suggests that it does.
*/
- { register int i; for (i = 0; i < 512*1024; i++) { } }
+ for (i = 0; i < 512*1024; i++) {
+ cpu_relax();
+ }
}
}
@@
-74,9
+77,10
@@
struct proc_dir_entry *pentry = NULL;
static inline void test(unsigned long arg, unsigned long arg2)
{
static inline void test(unsigned long arg, unsigned long arg2)
{
-
register
int temp[5];
+
volatile
int temp[5];
#ifdef CACHEFLUSH
#ifdef CACHEFLUSH
- pmc_flush_cache();
+ clflush(¤t->pid);
+ //pmc_flush_cache();
#endif
temp[2] = (temp[0] + 60) << 10;
temp[3] = (temp[2] + 60) << 10;
#endif
temp[2] = (temp[0] + 60) << 10;
temp[3] = (temp[2] + 60) << 10;
@@
-97,8
+101,8
@@
static int my_open(struct inode *inode, struct file *file)
local_irq_save(flags);
#ifdef CACHEFLUSH
local_irq_save(flags);
#ifdef CACHEFLUSH
-
pmc_flush_cache();
/* initial write back, without cycle count */
-
msleep(20);
/* wait for L2 flush */
+
//pmc_flush_cache();
/* initial write back, without cycle count */
+
//msleep(20);
/* wait for L2 flush */
#endif
rdtsc_barrier();
cycles1 = get_cycles();
#endif
rdtsc_barrier();
cycles1 = get_cycles();
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