9 * Copyright February 2009 - Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
11 * Credits for Paul e. McKenney <paulmck@linux.vnet.ibm.com>
12 * for inspiration coming from the Linux kernel RCU and rcu-preempt.
14 * The barrier, mb, rmb, wmb, atomic_inc, smp_read_barrier_depends, ACCESS_ONCE
15 * and rcu_dereference primitives come from the Linux kernel.
17 * Distributed under GPLv2
23 /* The "volatile" is due to gcc bugs */
24 #define barrier() __asm__ __volatile__("": : :"memory")
26 #define likely(x) __builtin_expect(!!(x), 1)
27 #define unlikely(x) __builtin_expect(!!(x), 0)
30 * Assume the architecture has coherent caches. Blackfin will want this unset.
32 #define CONFIG_HAVE_MEM_COHERENCY 1
34 /* Assume P4 or newer */
35 #define CONFIG_HAVE_FENCE 1
37 /* Assume SMP machine, given we don't have this information */
41 #ifdef CONFIG_HAVE_MEM_COHERENCY
43 * Caches are coherent, no need to flush them.
45 #define mc() barrier()
46 #define rmc() barrier()
47 #define wmc() barrier()
49 #error "The architecture must create its own cache flush primitives"
50 #define mc() arch_cache_flush()
51 #define rmc() arch_cache_flush_read()
52 #define wmc() arch_cache_flush_write()
56 #ifdef CONFIG_HAVE_MEM_COHERENCY
58 /* x86 32/64 specific */
59 #ifdef CONFIG_HAVE_FENCE
60 #define mb() asm volatile("mfence":::"memory")
61 #define rmb() asm volatile("lfence":::"memory")
62 #define wmb() asm volatile("sfence"::: "memory")
65 * Some non-Intel clones support out of order store. wmb() ceases to be a
68 #define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
69 #define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
70 #define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
73 #else /* !CONFIG_HAVE_MEM_COHERENCY */
76 * Without cache coherency, the memory barriers become cache flushes.
82 #endif /* !CONFIG_HAVE_MEM_COHERENCY */
87 #define smp_rmb() rmb()
88 #define smp_wmb() wmb()
90 #define smp_rmc() rmc()
91 #define smp_wmc() wmc()
93 #define smp_mb() barrier()
94 #define smp_rmb() barrier()
95 #define smp_wmb() barrier()
96 #define smp_mc() barrier()
97 #define smp_rmc() barrier()
98 #define smp_wmc() barrier()
101 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
102 static inline void rep_nop(void)
104 asm volatile("rep; nop" ::: "memory");
107 static inline void cpu_relax(void)
112 static inline void atomic_inc(int *v
)
114 asm volatile("lock; incl %0"
118 #define xchg(ptr, v) \
119 ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr))))
121 struct __xchg_dummy
{
122 unsigned long a
[100];
124 #define __xg(x) ((struct __xchg_dummy *)(x))
127 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
128 * Note 2: xchg has side effect, so that attribute volatile is necessary,
129 * but generally the primitive is invalid, *ptr is output argument. --ANK
130 * x is considered local, ptr is considered remote.
132 static inline unsigned long __xchg(unsigned long x
, volatile void *ptr
,
137 asm volatile("xchgb %b0,%1"
139 : "m" (*__xg(ptr
)), "0" (x
)
143 asm volatile("xchgw %w0,%1"
145 : "m" (*__xg(ptr
)), "0" (x
)
149 asm volatile("xchgl %k0,%1"
151 : "m" (*__xg(ptr
)), "0" (x
)
155 asm volatile("xchgq %0,%1"
157 : "m" (*__xg(ptr
)), "0" (x
)
165 /* Nop everywhere except on alpha. */
166 #define smp_read_barrier_depends()
169 * Prevent the compiler from merging or refetching accesses. The compiler
170 * is also forbidden from reordering successive instances of ACCESS_ONCE(),
171 * but only when the compiler is aware of some particular ordering. One way
172 * to make the compiler aware of ordering is to put the two invocations of
173 * ACCESS_ONCE() in different C statements.
175 * This macro does absolutely -nothing- to prevent the CPU from reordering,
176 * merging, or refetching absolutely anything at any time. Its main intended
177 * use is to mediate communication between process-level code and irq/NMI
178 * handlers, all running on the same CPU.
180 #define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
183 * Identify a shared load. A smp_rmc() or smp_mc() should come before the load.
185 #define _LOAD_SHARED(p) ACCESS_ONCE(p)
188 * Load a data from shared memory, doing a cache flush if required.
190 #define LOAD_SHARED(p) \
198 * Identify a shared store. A smp_wmc() or smp_mc() should follow the store.
200 #define _STORE_SHARED(x, v) \
206 * Store v into x, where x is located in shared memory. Performs the required
207 * cache flush after writing.
209 #define STORE_SHARED(x, v) \
211 _STORE_SHARED(x, v); \
216 * rcu_dereference - fetch an RCU-protected pointer in an
217 * RCU read-side critical section. This pointer may later
218 * be safely dereferenced.
220 * Inserts memory barriers on architectures that require them
221 * (currently only the Alpha), and, more importantly, documents
222 * exactly which pointers are protected by RCU.
225 #define rcu_dereference(p) ({ \
226 typeof(p) _________p1 = LOAD_SHARED(p); \
227 smp_read_barrier_depends(); \
231 #define SIGURCU SIGUSR1
234 * If a reader is really non-cooperative and refuses to commit its
235 * urcu_active_readers count to memory (there is no barrier in the reader
236 * per-se), kick it after a few loops waiting for it.
238 #define KICK_READER_LOOPS 10000
246 #define YIELD_READ (1 << 0)
247 #define YIELD_WRITE (1 << 1)
249 /* Updates without DEBUG_FULL_MB are much slower. Account this in the delay */
251 /* maximum sleep delay, in us */
254 #define MAX_SLEEP 30000
257 extern unsigned int yield_active
;
258 extern unsigned int __thread rand_yield
;
260 static inline void debug_yield_read(void)
262 if (yield_active
& YIELD_READ
)
263 if (rand_r(&rand_yield
) & 0x1)
264 usleep(rand_r(&rand_yield
) % MAX_SLEEP
);
267 static inline void debug_yield_write(void)
269 if (yield_active
& YIELD_WRITE
)
270 if (rand_r(&rand_yield
) & 0x1)
271 usleep(rand_r(&rand_yield
) % MAX_SLEEP
);
274 static inline void debug_yield_init(void)
276 rand_yield
= time(NULL
) ^ pthread_self();
279 static inline void debug_yield_read(void)
283 static inline void debug_yield_write(void)
287 static inline void debug_yield_init(void)
294 static inline void reader_barrier()
299 static inline void reader_barrier()
306 * The trick here is that RCU_GP_CTR_BIT must be a multiple of 8 so we can use a
307 * full 8-bits, 16-bits or 32-bits bitmask for the lower order bits.
309 #define RCU_GP_COUNT (1UL << 0)
310 /* Use the amount of bits equal to half of the architecture long size */
311 #define RCU_GP_CTR_BIT (1UL << (sizeof(long) << 2))
312 #define RCU_GP_CTR_NEST_MASK (RCU_GP_CTR_BIT - 1)
315 * Global quiescent period counter with low-order bits unused.
316 * Using a int rather than a char to eliminate false register dependencies
317 * causing stalls on some architectures.
319 extern long urcu_gp_ctr
;
321 extern long __thread urcu_active_readers
;
323 static inline int rcu_old_gp_ongoing(long *value
)
330 * Make sure both tests below are done on the same version of *value
331 * to insure consistency.
333 v
= LOAD_SHARED(*value
);
334 return (v
& RCU_GP_CTR_NEST_MASK
) &&
335 ((v
^ urcu_gp_ctr
) & RCU_GP_CTR_BIT
);
338 static inline void rcu_read_lock(void)
342 tmp
= urcu_active_readers
;
343 /* urcu_gp_ctr = RCU_GP_COUNT | (~RCU_GP_CTR_BIT or RCU_GP_CTR_BIT) */
345 * The data dependency "read urcu_gp_ctr, write urcu_active_readers",
346 * serializes those two memory operations. The memory barrier in the
347 * signal handler ensures we receive the proper memory commit barriers
348 * required by _STORE_SHARED and _LOAD_SHARED whenever communication
349 * with the writer is needed.
351 if (likely(!(tmp
& RCU_GP_CTR_NEST_MASK
)))
352 _STORE_SHARED(urcu_active_readers
, _LOAD_SHARED(urcu_gp_ctr
));
354 _STORE_SHARED(urcu_active_readers
, tmp
+ RCU_GP_COUNT
);
356 * Increment active readers count before accessing the pointer.
357 * See force_mb_all_threads().
362 static inline void rcu_read_unlock(void)
366 * Finish using rcu before decrementing the pointer.
367 * See force_mb_all_threads().
369 _STORE_SHARED(urcu_active_readers
, urcu_active_readers
- RCU_GP_COUNT
);
373 * rcu_assign_pointer - assign (publicize) a pointer to a newly
374 * initialized structure that will be dereferenced by RCU read-side
375 * critical sections. Returns the value assigned.
377 * Inserts memory barriers on architectures that require them
378 * (pretty much all of them other than x86), and also prevents
379 * the compiler from reordering the code that initializes the
380 * structure after the pointer assignment. More importantly, this
381 * call documents which pointers will be dereferenced by RCU read-side
385 #define rcu_assign_pointer(p, v) \
387 if (!__builtin_constant_p(v) || \
390 STORE_SHARED(p, v); \
393 #define rcu_xchg_pointer(p, v) \
395 if (!__builtin_constant_p(v) || \
401 extern void synchronize_rcu(void);
404 * Exchanges the pointer and waits for quiescent state.
405 * The pointer returned can be freed.
407 #define urcu_publish_content(p, v) \
410 oldptr = rcu_xchg_pointer(p, v); \
416 * Reader thread registration.
418 extern void urcu_register_thread(void);
419 extern void urcu_unregister_thread(void);