1 #ifndef _URCU_ARCH_UATOMIC_PPC_H
2 #define _URCU_ARCH_UATOMIC_PPC_H
5 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
6 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
7 * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
8 * Copyright (c) 2009 Mathieu Desnoyers
10 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
11 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
13 * Permission is hereby granted to use or copy this program
14 * for any purpose, provided the above notices are retained on all copies.
15 * Permission to modify the code and to distribute modified code is granted,
16 * provided the above notices are retained, and a notice that the code was
17 * modified is included with the above copyright notice.
19 * Code inspired from libuatomic_ops-1.2, inherited in part from the
20 * Boehm-Demers-Weiser conservative garbage collector.
23 #include <urcu/compiler.h>
24 #include <urcu/system.h>
30 #ifndef __SIZEOF_LONG__
32 #define __SIZEOF_LONG__ 8
34 #define __SIZEOF_LONG__ 4
39 #define LWSYNC_OPCODE "sync\n"
41 #define LWSYNC_OPCODE "lwsync\n"
45 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
48 #define ILLEGAL_INSTR ".long 0xd00d00"
50 #define uatomic_set(addr, v) STORE_SHARED(*(addr), (v))
51 #define uatomic_read(addr) LOAD_SHARED(*(addr))
54 * Using a isync as second barrier for exchange to provide acquire semantic.
55 * According to uatomic_ops/sysdeps/gcc/powerpc.h, the documentation is "fairly
56 * explicit that this also has acquire semantics."
57 * Derived from AO_compare_and_swap(), but removed the comparison.
62 static inline __attribute__((always_inline
))
63 unsigned long _uatomic_exchange(void *addr
, unsigned long val
, int len
)
72 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
73 "stwcx. %2,0,%1\n" /* else store conditional */
74 "bne- 1b\n" /* retry if lost reservation */
82 #if (BITS_PER_LONG == 64)
89 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
90 "stdcx. %2,0,%1\n" /* else store conditional */
91 "bne- 1b\n" /* retry if lost reservation */
101 /* generate an illegal instruction. Cannot catch this with linker tricks
102 * when optimizations are disabled. */
103 __asm__
__volatile__(ILLEGAL_INSTR
);
107 #define uatomic_xchg(addr, v) \
108 ((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
112 static inline __attribute__((always_inline
))
113 unsigned long _uatomic_cmpxchg(void *addr
, unsigned long old
,
114 unsigned long _new
, int len
)
119 unsigned int old_val
;
121 __asm__
__volatile__(
123 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
124 "cmpd %0,%3\n" /* if load is not equal to */
125 "bne 2f\n" /* old, fail */
126 "stwcx. %2,0,%1\n" /* else store conditional */
127 "bne- 1b\n" /* retry if lost reservation */
131 : "r"(addr
), "r"((unsigned int)_new
),
132 "r"((unsigned int)old
)
137 #if (BITS_PER_LONG == 64)
140 unsigned long old_val
;
142 __asm__
__volatile__(
144 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
145 "cmpd %0,%3\n" /* if load is not equal to */
146 "bne 2f\n" /* old, fail */
147 "stdcx. %2,0,%1\n" /* else store conditional */
148 "bne- 1b\n" /* retry if lost reservation */
152 : "r"(addr
), "r"((unsigned long)_new
),
153 "r"((unsigned long)old
)
160 /* generate an illegal instruction. Cannot catch this with linker tricks
161 * when optimizations are disabled. */
162 __asm__
__volatile__(ILLEGAL_INSTR
);
167 #define uatomic_cmpxchg(addr, old, _new) \
168 ((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
169 (unsigned long)(_new), \
172 /* uatomic_add_return */
174 static inline __attribute__((always_inline
))
175 unsigned long _uatomic_add_return(void *addr
, unsigned long val
,
183 __asm__
__volatile__(
185 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
186 "add %0,%2,%0\n" /* add val to value loaded */
187 "stwcx. %0,0,%1\n" /* store conditional */
188 "bne- 1b\n" /* retry if lost reservation */
191 : "r"(addr
), "r"(val
)
196 #if (BITS_PER_LONG == 64)
199 unsigned long result
;
201 __asm__
__volatile__(
203 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
204 "add %0,%2,%0\n" /* add val to value loaded */
205 "stdcx. %0,0,%1\n" /* store conditional */
206 "bne- 1b\n" /* retry if lost reservation */
209 : "r"(addr
), "r"(val
)
216 /* generate an illegal instruction. Cannot catch this with linker tricks
217 * when optimizations are disabled. */
218 __asm__
__volatile__(ILLEGAL_INSTR
);
223 #define uatomic_add_return(addr, v) \
224 ((__typeof__(*(addr))) _uatomic_add_return((addr), \
225 (unsigned long)(v), \
228 /* uatomic_sub_return, uatomic_add, uatomic_sub, uatomic_inc, uatomic_dec */
230 #define uatomic_sub_return(addr, v) uatomic_add_return((addr), -(v))
232 #define uatomic_add(addr, v) (void)uatomic_add_return((addr), (v))
233 #define uatomic_sub(addr, v) (void)uatomic_sub_return((addr), (v))
235 #define uatomic_inc(addr) uatomic_add((addr), 1)
236 #define uatomic_dec(addr) uatomic_add((addr), -1)
242 #endif /* _URCU_ARCH_UATOMIC_PPC_H */
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