66b27d5574df9d0b90820e0020282ec79616167f
1 #ifndef _URCU_ARCH_X86_H
2 #define _URCU_ARCH_X86_H
5 * arch_x86.h: trivial definitions for the x86 architecture.
7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <urcu/compiler.h>
27 /* Assume P4 or newer */
28 #define CONFIG_HAVE_FENCE 1
29 #define CONFIG_HAVE_MEM_COHERENCY
31 #define CACHE_LINE_SIZE 128
34 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
37 #ifdef CONFIG_HAVE_FENCE
38 #define mb() asm volatile("mfence":::"memory")
39 #define rmb() asm volatile("lfence":::"memory")
40 #define wmb() asm volatile("sfence"::: "memory")
43 * Some non-Intel clones support out of order store. wmb() ceases to be a
46 #define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
47 #define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory")
48 #define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory")
52 * Architectures without cache coherency need something like the following:
57 * #define mc() arch_cache_flush()
58 * #define rmc() arch_cache_flush_read()
59 * #define wmc() arch_cache_flush_write()
62 #define mc() barrier()
63 #define rmc() barrier()
64 #define wmc() barrier()
66 /* Assume SMP machine, given we don't have this information */
71 #define smp_rmb() rmb()
72 #define smp_wmb() wmb()
74 #define smp_rmc() rmc()
75 #define smp_wmc() wmc()
77 #define smp_mb() barrier()
78 #define smp_rmb() barrier()
79 #define smp_wmb() barrier()
80 #define smp_mc() barrier()
81 #define smp_rmc() barrier()
82 #define smp_wmc() barrier()
85 /* Nop everywhere except on alpha. */
86 #define smp_read_barrier_depends()
88 static inline void rep_nop(void)
90 asm volatile("rep; nop" : : : "memory");
93 static inline void cpu_relax(void)
99 * Serialize core instruction execution. Also acts as a compiler barrier.
103 * Cannot use cpuid because it clobbers the ebx register and clashes
105 * error: PIC register 'ebx' clobbered in 'asm'
107 static inline void sync_core(void)
112 static inline void sync_core(void)
114 asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
118 #define rdtscll(val) \
120 unsigned int __a, __d; \
121 asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
122 (val) = ((unsigned long long)__a) \
123 | (((unsigned long long)__d) << 32); \
126 typedef unsigned long long cycles_t
;
128 static inline cycles_t
get_cycles(void)
136 #endif /* _URCU_ARCH_X86_H */
This page took 0.032981 seconds and 4 git commands to generate.