urcu/arch_ppc.h

   1 #ifndef _URCU_ARCH_PPC_H
   2 #define _URCU_ARCH_PPC_H
   3
   4 /*
   5  * arch_ppc.h: trivial definitions for the powerpc architecture.
   6  *
   7  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
   8  * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
   9  *
  10  * This library is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU Lesser General Public
  12  * License as published by the Free Software Foundation; either
  13  * version 2.1 of the License, or (at your option) any later version.
  14 *
  15  * This library is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * Lesser General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU Lesser General Public
  21  * License along with this library; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  23  */
  24
  25 #include <urcu/compiler.h>
  26 #include <urcu/config.h>
  27
  28 #define CONFIG_HAVE_MEM_COHERENCY
  29
  30 /* Include size of POWER5+ L3 cache lines: 256 bytes */
  31 #define CACHE_LINE_SIZE 256
  32
  33 #ifndef BITS_PER_LONG
  34 #define BITS_PER_LONG   (__SIZEOF_LONG__ * 8)
  35 #endif
  36
  37 #define mb()    asm volatile("sync":::"memory")
  38 #define rmb()   asm volatile("sync":::"memory")
  39 #define wmb()   asm volatile("sync"::: "memory")
  40
  41 /*
  42  * Architectures without cache coherency need something like the following:
  43  *
  44  * #define mb()         mc()
  45  * #define rmb()        rmc()
  46  * #define wmb()        wmc()
  47  * #define mc()         arch_cache_flush()
  48  * #define rmc()        arch_cache_flush_read()
  49  * #define wmc()        arch_cache_flush_write()
  50  */
  51
  52 #define mc()    barrier()
  53 #define rmc()   barrier()
  54 #define wmc()   barrier()
  55
  56 #ifdef CONFIG_URCU_SMP
  57 #define smp_mb()        mb()
  58 #define smp_rmb()       rmb()
  59 #define smp_wmb()       wmb()
  60 #define smp_mc()        mc()
  61 #define smp_rmc()       rmc()
  62 #define smp_wmc()       wmc()
  63 #else
  64 #define smp_mb()        barrier()
  65 #define smp_rmb()       barrier()
  66 #define smp_wmb()       barrier()
  67 #define smp_mc()        barrier()
  68 #define smp_rmc()       barrier()
  69 #define smp_wmc()       barrier()
  70 #endif
  71
  72 /* Nop everywhere except on alpha. */
  73 #define smp_read_barrier_depends()
  74
  75 static inline void cpu_relax(void)
  76 {
  77         barrier();
  78 }
  79
  80 /*
  81  * Serialize core instruction execution. Also acts as a compiler barrier.
  82  */
  83 static inline void sync_core()
  84 {
  85         asm volatile("isync" : : : "memory");
  86 }
  87
  88 #define mftbl()                                         \
  89         ({                                              \
  90                 unsigned long rval;                     \
  91                 asm volatile("mftbl %0" : "=r" (rval)); \
  92                 rval;                                   \
  93         })
  94
  95 #define mftbu()                                         \
  96         ({                                              \
  97                 unsigned long rval;                     \
  98                 asm volatile("mftbu %0" : "=r" (rval)); \
  99                 rval;                                   \
 100         })
 101
 102 typedef unsigned long long cycles_t;
 103
 104 static inline cycles_t get_cycles (void)
 105 {
 106         long h, l;
 107
 108         for (;;) {
 109                 h = mftbu();
 110                 barrier();
 111                 l = mftbl();
 112                 barrier();
 113                 if (mftbu() == h)
 114                         return (((cycles_t) h) << 32) + l;
 115         }
 116 }
 117
 118 #endif /* _URCU_ARCH_PPC_H */