urcu/arch/ppc.h

   1 #ifndef _URCU_ARCH_PPC_H
   2 #define _URCU_ARCH_PPC_H
   3
   4 /*
   5  * arch_ppc.h: trivial definitions for the powerpc architecture.
   6  *
   7  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
   8  * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
   9  *
  10  * This library is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU Lesser General Public
  12  * License as published by the Free Software Foundation; either
  13  * version 2.1 of the License, or (at your option) any later version.
  14  *
  15  * This library is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * Lesser General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU Lesser General Public
  21  * License along with this library; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  23  */
  24
  25 #include <urcu/compiler.h>
  26 #include <urcu/config.h>
  27 #include <urcu/syscall-compat.h>
  28 #include <stdint.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* Include size of POWER5+ L3 cache lines: 256 bytes */
  35 #define CAA_CACHE_LINE_SIZE     256
  36
  37 #ifdef __NO_LWSYNC__
  38 #define LWSYNC_OPCODE   "sync\n"
  39 #else
  40 #define LWSYNC_OPCODE   "lwsync\n"
  41 #endif
  42
  43 /*
  44  * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
  45  * preserve ordering of cacheable vs. non-cacheable accesses, so it
  46  * should not be used to order with respect to MMIO operations.  An
  47  * eieio+lwsync pair is also not enough for cmm_rmb, because it will
  48  * order cacheable and non-cacheable memory operations separately---i.e.
  49  * not the latter against the former.
  50  */
  51 #define cmm_mb()         __asm__ __volatile__ ("sync":::"memory")
  52
  53 /*
  54  * lwsync orders loads in cacheable memory with respect to other loads,
  55  * and stores in cacheable memory with respect to other stores.
  56  * Therefore, use it for barriers ordering accesses to cacheable memory
  57  * only.
  58  */
  59 #define cmm_smp_rmb()    __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
  60 #define cmm_smp_wmb()    __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
  61
  62 #define mftbl()                                         \
  63         __extension__                                   \
  64         ({                                              \
  65                 unsigned long rval;                     \
  66                 __asm__ __volatile__ ("mftbl %0" : "=r" (rval));        \
  67                 rval;                                   \
  68         })
  69
  70 #define mftbu()                                         \
  71         __extension__                                   \
  72         ({                                              \
  73                 unsigned long rval;                     \
  74                 __asm__ __volatile__ ("mftbu %0" : "=r" (rval));        \
  75                 rval;                                   \
  76         })
  77
  78 #define mftb()                                          \
  79         __extension__                                   \
  80         ({                                              \
  81                 unsigned long long rval;                \
  82                 __asm__ __volatile__ ("mftb %0" : "=r" (rval));         \
  83                 rval;                                   \
  84         })
  85
  86 #define HAS_CAA_GET_CYCLES
  87
  88 typedef uint64_t caa_cycles_t;
  89
  90 #ifdef __powerpc64__
  91 static inline caa_cycles_t caa_get_cycles(void)
  92 {
  93         return (caa_cycles_t) mftb();
  94 }
  95 #else
  96 static inline caa_cycles_t caa_get_cycles(void)
  97 {
  98         unsigned long h, l;
  99
 100         for (;;) {
 101                 h = mftbu();
 102                 cmm_barrier();
 103                 l = mftbl();
 104                 cmm_barrier();
 105                 if (mftbu() == h)
 106                         return (((caa_cycles_t) h) << 32) + l;
 107         }
 108 }
 109 #endif
 110
 111 /*
 112  * Define the membarrier system call number if not yet available in the
 113  * system headers.
 114  */
 115 #ifndef __NR_membarrier
 116 #define __NR_membarrier         365
 117 #endif
 118
 119 #ifdef __cplusplus
 120 }
 121 #endif
 122
 123 #include <urcu/arch/generic.h>
 124
 125 #endif /* _URCU_ARCH_PPC_H */