urcu/arch/ppc.h

   1 #ifndef _URCU_ARCH_PPC_H
   2 #define _URCU_ARCH_PPC_H
   3
   4 /*
   5  * arch_ppc.h: trivial definitions for the powerpc architecture.
   6  *
   7  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
   8  * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
   9  *
  10  * This library is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU Lesser General Public
  12  * License as published by the Free Software Foundation; either
  13  * version 2.1 of the License, or (at your option) any later version.
  14  *
  15  * This library is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * Lesser General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU Lesser General Public
  21  * License along with this library; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  23  */
  24
  25 #include <urcu/compiler.h>
  26 #include <urcu/config.h>
  27
  28 #ifdef __cplusplus
  29 extern "C" {
  30 #endif
  31
  32 /* Include size of POWER5+ L3 cache lines: 256 bytes */
  33 #define CAA_CACHE_LINE_SIZE     256
  34
  35 #ifdef __NO_LWSYNC__
  36 #define LWSYNC_OPCODE   "sync\n"
  37 #else
  38 #define LWSYNC_OPCODE   "lwsync\n"
  39 #endif
  40
  41 /*
  42  * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
  43  * preserve ordering of cacheable vs. non-cacheable accesses, so it
  44  * should not be used to order with respect to MMIO operations.  An
  45  * eieio+lwsync pair is also not enough for cmm_rmb, because it will
  46  * order cacheable and non-cacheable memory operations separately---i.e.
  47  * not the latter against the former.
  48  */
  49 #define cmm_mb()         asm volatile("sync":::"memory")
  50
  51 /*
  52  * lwsync orders loads in cacheable memory with respect to other loads,
  53  * and stores in cacheable memory with respect to other stores.
  54  * Therefore, use it for barriers ordering accesses to cacheable memory
  55  * only.
  56  */
  57 #define cmm_smp_rmb()    asm volatile(LWSYNC_OPCODE:::"memory")
  58 #define cmm_smp_wmb()    asm volatile(LWSYNC_OPCODE:::"memory")
  59
  60 #define mftbl()                                         \
  61         ({                                              \
  62                 unsigned long rval;                     \
  63                 asm volatile("mftbl %0" : "=r" (rval)); \
  64                 rval;                                   \
  65         })
  66
  67 #define mftbu()                                         \
  68         ({                                              \
  69                 unsigned long rval;                     \
  70                 asm volatile("mftbu %0" : "=r" (rval)); \
  71                 rval;                                   \
  72         })
  73
  74 #define mftb()                                          \
  75         ({                                              \
  76                 unsigned long long rval;                \
  77                 asm volatile("mftb %0" : "=r" (rval));  \
  78                 rval;                                   \
  79         })
  80
  81 typedef unsigned long long cycles_t;
  82
  83 #ifdef __powerpc64__
  84 static inline cycles_t caa_get_cycles(void)
  85 {
  86         return (cycles_t) mftb();
  87 }
  88 #else
  89 static inline cycles_t caa_get_cycles(void)
  90 {
  91         unsigned long h, l;
  92
  93         for (;;) {
  94                 h = mftbu();
  95                 cmm_barrier();
  96                 l = mftbl();
  97                 cmm_barrier();
  98                 if (mftbu() == h)
  99                         return (((cycles_t) h) << 32) + l;
 100         }
 101 }
 102 #endif
 103
 104 #ifdef __cplusplus
 105 }
 106 #endif
 107
 108 #include <urcu/arch/generic.h>
 109
 110 #endif /* _URCU_ARCH_PPC_H */