urcu/arch/ppc.h

   1 #ifndef _URCU_ARCH_PPC_H
   2 #define _URCU_ARCH_PPC_H
   3
   4 /*
   5  * arch_ppc.h: trivial definitions for the powerpc architecture.
   6  *
   7  * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
   8  * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
   9  *
  10  * This library is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU Lesser General Public
  12  * License as published by the Free Software Foundation; either
  13  * version 2.1 of the License, or (at your option) any later version.
  14  *
  15  * This library is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * Lesser General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU Lesser General Public
  21  * License along with this library; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  23  */
  24
  25 #include <urcu/compiler.h>
  26 #include <urcu/config.h>
  27
  28 #ifdef __cplusplus
  29 extern "C" {
  30 #endif
  31
  32 /* Include size of POWER5+ L3 cache lines: 256 bytes */
  33 #define CAA_CACHE_LINE_SIZE     256
  34
  35 /*
  36  * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
  37  * preserve ordering of cacheable vs. non-cacheable accesses, so it
  38  * should not be used to order with respect to MMIO operations.  An
  39  * eieio+lwsync pair is also not enough for cmm_rmb, because it will
  40  * order cacheable and non-cacheable memory operations separately---i.e.
  41  * not the latter against the former.
  42  */
  43 #define cmm_mb()         asm volatile("sync":::"memory")
  44
  45 /*
  46  * lwsync orders loads in cacheable memory with respect to other loads,
  47  * and stores in cacheable memory with respect to other stores.
  48  * Therefore, use it for barriers ordering accesses to cacheable memory
  49  * only.
  50  */
  51 #define cmm_smp_rmb()    asm volatile("lwsync":::"memory")
  52 #define cmm_smp_wmb()    asm volatile("lwsync":::"memory")
  53
  54 #define mftbl()                                         \
  55         ({                                              \
  56                 unsigned long rval;                     \
  57                 asm volatile("mftbl %0" : "=r" (rval)); \
  58                 rval;                                   \
  59         })
  60
  61 #define mftbu()                                         \
  62         ({                                              \
  63                 unsigned long rval;                     \
  64                 asm volatile("mftbu %0" : "=r" (rval)); \
  65                 rval;                                   \
  66         })
  67
  68 #define mftb()                                          \
  69         ({                                              \
  70                 unsigned long long rval;                \
  71                 asm volatile("mftb %0" : "=r" (rval));  \
  72                 rval;                                   \
  73         })
  74
  75 typedef unsigned long long cycles_t;
  76
  77 #ifdef __powerpc64__
  78 static inline cycles_t caa_get_cycles(void)
  79 {
  80         return (cycles_t) mftb();
  81 }
  82 #else
  83 static inline cycles_t caa_get_cycles(void)
  84 {
  85         unsigned long h, l;
  86
  87         for (;;) {
  88                 h = mftbu();
  89                 cmm_barrier();
  90                 l = mftbl();
  91                 cmm_barrier();
  92                 if (mftbu() == h)
  93                         return (((cycles_t) h) << 32) + l;
  94         }
  95 }
  96 #endif
  97
  98 #ifdef __cplusplus
  99 }
 100 #endif
 101
 102 #include <urcu/arch/generic.h>
 103
 104 #endif /* _URCU_ARCH_PPC_H */