31807505c271fc0a1e6eea5400a529585ea8935a
1 #ifndef _URCU_ARCH_UATOMIC_PPC_H
2 #define _URCU_ARCH_UATOMIC_PPC_H
5 * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
6 * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
7 * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
8 * Copyright (c) 2009 Mathieu Desnoyers
10 * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
11 * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
13 * Permission is hereby granted to use or copy this program
14 * for any purpose, provided the above notices are retained on all copies.
15 * Permission to modify the code and to distribute modified code is granted,
16 * provided the above notices are retained, and a notice that the code was
17 * modified is included with the above copyright notice.
19 * Code inspired from libuatomic_ops-1.2, inherited in part from the
20 * Boehm-Demers-Weiser conservative garbage collector.
23 #include <urcu/compiler.h>
24 #include <urcu/system.h>
30 #define ILLEGAL_INSTR ".long 0xd00d00"
33 * Providing sequential consistency semantic with respect to other
34 * instructions for cmpxchg and add_return family of atomic primitives.
36 * This is achieved with:
37 * lwsync (prior loads can be reordered after following load)
40 * test if success (retry)
43 * Explanation of the sequential consistency provided by this scheme
44 * from Paul E. McKenney:
46 * The reason we can get away with the lwsync before is that if a prior
47 * store reorders with the lwarx, then you have to store to the atomic
48 * variable from some other CPU to detect it.
50 * And if you do that, the lwarx will lose its reservation, so the stwcx
51 * will fail. The atomic operation will retry, so that the caller won't be
52 * able to see the misordering.
57 static inline __attribute__((always_inline
))
58 unsigned long _uatomic_exchange(void *addr
, unsigned long val
, int len
)
67 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
68 "stwcx. %2,0,%1\n" /* else store conditional */
69 "bne- 1b\n" /* retry if lost reservation */
77 #if (CAA_BITS_PER_LONG == 64)
84 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
85 "stdcx. %2,0,%1\n" /* else store conditional */
86 "bne- 1b\n" /* retry if lost reservation */
96 /* generate an illegal instruction. Cannot catch this with linker tricks
97 * when optimizations are disabled. */
98 __asm__
__volatile__(ILLEGAL_INSTR
);
102 #define uatomic_xchg(addr, v) \
103 ((__typeof__(*(addr))) _uatomic_exchange((addr), (unsigned long)(v), \
107 static inline __attribute__((always_inline
))
108 unsigned long _uatomic_cmpxchg(void *addr
, unsigned long old
,
109 unsigned long _new
, int len
)
114 unsigned int old_val
;
116 __asm__
__volatile__(
118 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
119 "cmpw %0,%3\n" /* if load is not equal to */
120 "bne 2f\n" /* old, fail */
121 "stwcx. %2,0,%1\n" /* else store conditional */
122 "bne- 1b\n" /* retry if lost reservation */
126 : "r"(addr
), "r"((unsigned int)_new
),
127 "r"((unsigned int)old
)
132 #if (CAA_BITS_PER_LONG == 64)
135 unsigned long old_val
;
137 __asm__
__volatile__(
139 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
140 "cmpd %0,%3\n" /* if load is not equal to */
141 "bne 2f\n" /* old, fail */
142 "stdcx. %2,0,%1\n" /* else store conditional */
143 "bne- 1b\n" /* retry if lost reservation */
147 : "r"(addr
), "r"((unsigned long)_new
),
148 "r"((unsigned long)old
)
155 /* generate an illegal instruction. Cannot catch this with linker tricks
156 * when optimizations are disabled. */
157 __asm__
__volatile__(ILLEGAL_INSTR
);
162 #define uatomic_cmpxchg(addr, old, _new) \
163 ((__typeof__(*(addr))) _uatomic_cmpxchg((addr), (unsigned long)(old),\
164 (unsigned long)(_new), \
167 /* uatomic_add_return */
169 static inline __attribute__((always_inline
))
170 unsigned long _uatomic_add_return(void *addr
, unsigned long val
,
178 __asm__
__volatile__(
180 "1:\t" "lwarx %0,0,%1\n" /* load and reserve */
181 "add %0,%2,%0\n" /* add val to value loaded */
182 "stwcx. %0,0,%1\n" /* store conditional */
183 "bne- 1b\n" /* retry if lost reservation */
186 : "r"(addr
), "r"(val
)
191 #if (CAA_BITS_PER_LONG == 64)
194 unsigned long result
;
196 __asm__
__volatile__(
198 "1:\t" "ldarx %0,0,%1\n" /* load and reserve */
199 "add %0,%2,%0\n" /* add val to value loaded */
200 "stdcx. %0,0,%1\n" /* store conditional */
201 "bne- 1b\n" /* retry if lost reservation */
204 : "r"(addr
), "r"(val
)
211 /* generate an illegal instruction. Cannot catch this with linker tricks
212 * when optimizations are disabled. */
213 __asm__
__volatile__(ILLEGAL_INSTR
);
218 #define uatomic_add_return(addr, v) \
219 ((__typeof__(*(addr))) _uatomic_add_return((addr), \
220 (unsigned long)(v), \
227 #include <urcu/uatomic/generic.h>
229 #endif /* _URCU_ARCH_UATOMIC_PPC_H */
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