32de6a8bbbb520e9e6d2febb3d9dfb12b59cff16
1 // SPDX-FileCopyrightText: 2021 Michael Jeanson <mjeanson@efficios.com>
3 // SPDX-License-Identifier: MIT
5 #ifndef _LTTNG_UST_ARCH_H
6 #define _LTTNG_UST_ARCH_H
9 * Architecture detection using compiler defines.
11 * The following defines are used internally for architecture specific code.
13 * LTTNG_UST_ARCH_X86 : All x86 variants 32 and 64 bits
14 * LTTNG_UST_ARCH_I386 : Specific to the i386
15 * LTTNG_UST_ARCH_AMD64 : All 64 bits x86 variants
16 * LTTNG_UST_ARCH_K1OM : Specific to the Xeon Phi / MIC
18 * LTTNG_UST_ARCH_PPC : All PowerPC variants 32 and 64 bits
19 * LTTNG_UST_ARCH_PPC64 : Specific to 64 bits variants
21 * LTTNG_UST_ARCH_S390 : All IBM s390 / s390x variants
23 * LTTNG_UST_ARCH_SPARC64 : All Sun SPARC variants
25 * LTTNG_UST_ARCH_ALPHA : All DEC Alpha variants
26 * LTTNG_UST_ARCH_IA64 : All Intel Itanium variants
27 * LTTNG_UST_ARCH_ARM : All ARM 32 bits variants
28 * LTTNG_UST_ARCH_ARMV7 : All ARMv7 ISA variants
29 * LTTNG_UST_ARCH_AARCH64 : All ARM 64 bits variants
30 * LTTNG_UST_ARCH_MIPS : All MIPS variants
31 * LTTNG_UST_ARCH_NIOS2 : All Intel / Altera NIOS II variants
32 * LTTNG_UST_ARCH_TILE : All Tilera TILE variants
33 * LTTNG_UST_ARCH_HPPA : All HP PA-RISC variants
34 * LTTNG_UST_ARCH_M68K : All Motorola 68000 variants
35 * LTTNG_UST_ARCH_RISCV : All RISC-V variants
38 #if (defined(__INTEL_OFFLOAD) || defined(__TARGET_ARCH_MIC) || defined(__MIC__))
40 #define LTTNG_UST_ARCH_X86 1
41 #define LTTNG_UST_ARCH_AMD64 1
42 #define LTTNG_UST_ARCH_K1OM 1
44 #elif (defined(__amd64__) || defined(__amd64) || defined(__x86_64__) || defined(__x86_64))
46 #define LTTNG_UST_ARCH_X86 1
47 #define LTTNG_UST_ARCH_AMD64 1
49 #elif (defined(__i486__) || defined(__i586__) || defined(__i686__))
51 #define LTTNG_UST_ARCH_X86 1
53 #elif (defined(__i386__) || defined(__i386))
55 #define LTTNG_UST_ARCH_X86 1
56 #define LTTNG_UST_ARCH_I386 1
58 #elif (defined(__powerpc64__) || defined(__ppc64__))
60 #define LTTNG_UST_ARCH_PPC 1
61 #define LTTNG_UST_ARCH_PPC64 1
63 #elif (defined(__powerpc__) || defined(__powerpc) || defined(__ppc__))
65 #define LTTNG_UST_ARCH_PPC 1
67 #elif (defined(__s390__) || defined(__s390x__) || defined(__zarch__))
69 #define LTTNG_UST_ARCH_S390 1
71 #elif (defined(__sparc__) || defined(__sparc) || defined(__sparc64__))
73 #define LTTNG_UST_ARCH_SPARC64 1
75 #elif (defined(__alpha__) || defined(__alpha))
77 #define LTTNG_UST_ARCH_ALPHA 1
79 #elif (defined(__ia64__) || defined(__ia64))
81 #define LTTNG_UST_ARCH_IA64 1
83 #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7__))
85 #define LTTNG_UST_ARCH_ARMV7 1
86 #define LTTNG_UST_ARCH_ARM 1
88 #elif (defined(__arm__) || defined(__arm))
90 #define LTTNG_UST_ARCH_ARM 1
92 #elif defined(__aarch64__)
94 #define LTTNG_UST_ARCH_AARCH64 1
96 #elif (defined(__mips__) || defined(__mips))
98 #define LTTNG_UST_ARCH_MIPS 1
100 #elif (defined(__nios2__) || defined(__nios2))
102 #define LTTNG_UST_ARCH_NIOS2 1
104 #elif (defined(__tile__) || defined(__tilegx__))
106 #define LTTNG_UST_ARCH_TILE 1
108 #elif (defined(__hppa__) || defined(__HPPA__) || defined(__hppa))
110 #define LTTNG_UST_ARCH_HPPA 1
112 #elif defined(__m68k__)
114 #define LTTNG_UST_ARCH_M68K 1
116 #elif defined(__riscv)
118 #define LTTNG_UST_ARCH_RISCV 1
122 /* Unrecognised architecture, use safe defaults */
123 #define LTTNG_UST_ARCH_UNKNOWN 1
129 * Per architecture global settings.
131 * LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS:
132 * The architecture has working and efficient unaligned memory access, the
133 * content of the ringbuffers will packed instead of following the natural
134 * alignment of the architecture.
137 #if defined(LTTNG_UST_ARCH_X86)
138 #define LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS 1
141 #if defined(LTTNG_UST_ARCH_PPC)
142 #define LTTNG_UST_ARCH_HAS_EFFICIENT_UNALIGNED_ACCESS 1
145 #endif /* _LTTNG_UST_ARCH_H */
This page took 0.034491 seconds and 5 git commands to generate.