2 * mem.spin: Promela code to validate memory barriers with OOO memory.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright (c) 2009 Mathieu Desnoyers
21 /* Promela validation variables. */
28 #define get_pid() (_pid)
31 * Each process have its own data in cache. Caches are randomly updated.
32 * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces
36 #define DECLARE_CACHED_VAR(type, x, v) \
38 type cached_##x[NR_PROCS] = v; \
39 bit cache_dirty_##x[NR_PROCS] = 0
41 #define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id])
43 #define READ_CACHED_VAR(x) (cached_##x[get_pid()])
45 #define WRITE_CACHED_VAR(x, v) \
47 cached_##x[get_pid()] = v; \
48 cache_dirty_##x[get_pid()] = 1; \
51 #define CACHE_WRITE_TO_MEM(x, id) \
53 :: IS_CACHE_DIRTY(x, id) -> \
54 mem_##x = cached_##x[id]; \
55 cache_dirty_##x[id] = 0; \
60 #define CACHE_READ_FROM_MEM(x, id) \
62 :: !IS_CACHE_DIRTY(x, id) -> \
63 cached_##x[id] = mem_##x;\
69 * May update other caches if cache is dirty, or not.
71 #define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
73 :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
77 #define RANDOM_CACHE_READ_FROM_MEM(x, id)\
79 :: 1 -> CACHE_READ_FROM_MEM(x, id); \
84 * Remote barriers tests the scheme where a signal (or IPI) is sent to all
85 * reader threads to promote their compiler barrier to a smp_mb().
87 #ifdef REMOTE_BARRIERS
92 CACHE_READ_FROM_MEM(urcu_gp_ctr, i);
93 CACHE_READ_FROM_MEM(urcu_active_readers_one, i);
94 CACHE_READ_FROM_MEM(generation_ptr, i);
101 CACHE_WRITE_TO_MEM(urcu_gp_ctr, i);
102 CACHE_WRITE_TO_MEM(urcu_active_readers_one, i);
103 CACHE_WRITE_TO_MEM(generation_ptr, i);
121 * Readers do a simple barrier(), writers are doing a smp_mb() _and_ sending a
122 * signal or IPI to have all readers execute a smp_mb.
123 * We are not modeling the whole rendez-vous between readers and writers here,
124 * we just let the writer update each reader's caches remotely.
129 :: get_pid() >= NR_READERS ->
130 smp_mb_pid(get_pid());
136 :: i >= NR_READERS -> break
138 smp_mb_pid(get_pid());
148 CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
149 CACHE_READ_FROM_MEM(urcu_active_readers_one, get_pid());
150 CACHE_READ_FROM_MEM(generation_ptr, get_pid());
157 CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
158 CACHE_WRITE_TO_MEM(urcu_active_readers_one, get_pid());
159 CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
178 /* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
179 DECLARE_CACHED_VAR(byte, urcu_gp_ctr, 1);
180 /* Note ! currently only one reader */
181 DECLARE_CACHED_VAR(byte, urcu_active_readers_one, 0);
182 /* pointer generation */
183 DECLARE_CACHED_VAR(byte, generation_ptr, 0);
185 byte last_free_gen = 0;
187 byte read_generation = 1;
195 RANDOM_CACHE_WRITE_TO_MEM(urcu_gp_ctr, get_pid());
196 RANDOM_CACHE_WRITE_TO_MEM(urcu_active_readers_one,
198 RANDOM_CACHE_WRITE_TO_MEM(generation_ptr, get_pid());
199 RANDOM_CACHE_READ_FROM_MEM(urcu_gp_ctr, get_pid());
200 RANDOM_CACHE_READ_FROM_MEM(urcu_active_readers_one,
202 RANDOM_CACHE_READ_FROM_MEM(generation_ptr, get_pid());
206 #define get_readerid() (get_pid())
207 #define get_writerid() (get_readerid() + NR_READERS)
209 inline wait_for_reader(tmp, id, i)
214 tmp = READ_CACHED_VAR(urcu_active_readers_one);
217 :: (tmp & RCU_GP_CTR_NEST_MASK)
218 && ((tmp ^ READ_CACHED_VAR(urcu_gp_ctr))
220 #ifndef GEN_ERROR_WRITER_PROGRESS
231 inline wait_for_quiescent_state(tmp, i, j)
236 wait_for_reader(tmp, i, j);
238 :: i >= NR_READERS -> break
242 /* Model the RCU read-side critical section. */
244 inline urcu_one_read(i, nest_i, tmp, tmp2)
248 :: nest_i < READER_NEST_LEVEL ->
250 tmp = READ_CACHED_VAR(urcu_active_readers_one);
253 :: (!(tmp & RCU_GP_CTR_NEST_MASK))
255 tmp2 = READ_CACHED_VAR(urcu_gp_ctr);
257 WRITE_CACHED_VAR(urcu_active_readers_one, tmp2);
259 WRITE_CACHED_VAR(urcu_active_readers_one,
265 :: nest_i >= READER_NEST_LEVEL -> break;
269 read_generation = READ_CACHED_VAR(generation_ptr);
277 :: nest_i < READER_NEST_LEVEL ->
281 tmp2 = READ_CACHED_VAR(urcu_active_readers_one);
283 WRITE_CACHED_VAR(urcu_active_readers_one, tmp2 - 1);
285 :: nest_i >= READER_NEST_LEVEL -> break;
288 //smp_mc(i); /* added */
291 active [NR_READERS] proctype urcu_reader()
296 assert(get_pid() < NR_PROCS);
302 * We do not test reader's progress here, because we are mainly
303 * interested in writer's progress. The reader never blocks
304 * anyway. We have to test for reader/writer's progress
305 * separately, otherwise we could think the writer is doing
306 * progress when it's blocked by an always progressing reader.
308 #ifdef READER_PROGRESS
311 urcu_one_read(i, nest_i, tmp, tmp2);
315 /* Model the RCU update process. */
317 active [NR_WRITERS] proctype urcu_writer()
323 assert(get_pid() < NR_PROCS);
326 :: (READ_CACHED_VAR(generation_ptr) < 5) ->
327 #ifdef WRITER_PROGRESS
332 old_gen = READ_CACHED_VAR(generation_ptr);
333 WRITE_CACHED_VAR(generation_ptr, old_gen + 1);
341 :: write_lock == 0 ->
351 tmp = READ_CACHED_VAR(urcu_gp_ctr);
353 WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
356 wait_for_quiescent_state(tmp, i, j);
360 tmp = READ_CACHED_VAR(urcu_gp_ctr);
362 WRITE_CACHED_VAR(urcu_gp_ctr, tmp ^ RCU_GP_CTR_BIT);
365 wait_for_quiescent_state(tmp, i, j);
371 /* free-up step, e.g., kfree(). */
373 last_free_gen = old_gen;
379 * Given the reader loops infinitely, let the writer also busy-loop
380 * with progress here so, with weak fairness, we can test the
386 #ifdef WRITER_PROGRESS