2 * mem.spin: Promela code to validate memory barriers with OOO memory.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright (c) 2009 Mathieu Desnoyers
22 * Out-of-order memory model _without_ out-of-order instruction scheduling.
25 /* Promela validation variables. */
32 #define get_pid() (_pid)
35 * Each process have its own data in cache. Caches are randomly updated.
36 * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces
40 #define DECLARE_CACHED_VAR(type, x, v) \
42 type cached_##x[NR_PROCS] = v; \
43 bit cache_dirty_##x[NR_PROCS] = 0
45 #define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id])
47 #define READ_CACHED_VAR(x) (cached_##x[get_pid()])
49 #define WRITE_CACHED_VAR(x, v) \
51 cached_##x[get_pid()] = v; \
52 cache_dirty_##x[get_pid()] = 1; \
55 #define CACHE_WRITE_TO_MEM(x, id) \
57 :: IS_CACHE_DIRTY(x, id) -> \
58 mem_##x = cached_##x[id]; \
59 cache_dirty_##x[id] = 0; \
64 #define CACHE_READ_FROM_MEM(x, id) \
66 :: !IS_CACHE_DIRTY(x, id) -> \
67 cached_##x[id] = mem_##x;\
73 * May update other caches if cache is dirty, or not.
75 #define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
77 :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
81 #define RANDOM_CACHE_READ_FROM_MEM(x, id)\
83 :: 1 -> CACHE_READ_FROM_MEM(x, id); \
90 CACHE_READ_FROM_MEM(alpha, get_pid());
91 CACHE_READ_FROM_MEM(beta, get_pid());
98 CACHE_WRITE_TO_MEM(alpha, get_pid());
99 CACHE_WRITE_TO_MEM(beta, get_pid());
111 /* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
112 DECLARE_CACHED_VAR(byte, alpha, 0);
113 DECLARE_CACHED_VAR(byte, beta, 0);
118 RANDOM_CACHE_WRITE_TO_MEM(alpha, get_pid());
119 RANDOM_CACHE_WRITE_TO_MEM(beta, get_pid());
120 RANDOM_CACHE_READ_FROM_MEM(alpha, get_pid());
121 RANDOM_CACHE_READ_FROM_MEM(beta, get_pid());
125 #define get_readerid() (get_pid())
127 byte first_read[NR_READERS];
128 byte second_read[NR_READERS];
130 active [NR_READERS] proctype test_reader()
132 assert(get_pid() < NR_PROCS);
135 first_read[get_readerid()] = READ_CACHED_VAR(beta);
141 second_read[get_readerid()] = READ_CACHED_VAR(alpha);
143 // test : [] (first_read == 6 -> <> second_read == 4)
144 assert(first_read[get_readerid()] != 6
145 || second_read[get_readerid()] == 4);
148 #define get_writerid() (get_readerid() + NR_READERS)
150 active [NR_WRITERS] proctype test_writer()
154 assert(get_pid() < NR_PROCS);
157 WRITE_CACHED_VAR(alpha, 4);
163 WRITE_CACHED_VAR(beta, 6);