2 * mem.spin: Promela code to validate memory barriers with OOO memory.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright (c) 2009 Mathieu Desnoyers
21 /* Promela validation variables. */
28 #define get_pid() (_pid)
31 * Each process have its own data in cache. Caches are randomly updated.
32 * smp_wmb and smp_rmb forces cache updates (write and read), wmb_mb forces
36 #define DECLARE_CACHED_VAR(type, x, v) \
38 type cached_##x[NR_PROCS] = v; \
39 bit cache_dirty_##x[NR_PROCS] = 0
41 #define IS_CACHE_DIRTY(x, id) (cache_dirty_##x[id])
43 #define READ_CACHED_VAR(x) (cached_##x[get_pid()])
45 #define WRITE_CACHED_VAR(x, v) \
47 cached_##x[get_pid()] = v; \
48 cache_dirty_##x[get_pid()] = 1; \
51 #define CACHE_WRITE_TO_MEM(x, id) \
53 :: IS_CACHE_DIRTY(x, id) -> \
54 mem_##x = cached_##x[id]; \
55 cache_dirty_##x[id] = 0; \
60 #define CACHE_READ_FROM_MEM(x, id) \
62 :: !IS_CACHE_DIRTY(x, id) -> \
63 cached_##x[id] = mem_##x;\
69 * May update other caches if cache is dirty, or not.
71 #define RANDOM_CACHE_WRITE_TO_MEM(x, id)\
73 :: 1 -> CACHE_WRITE_TO_MEM(x, id); \
77 #define RANDOM_CACHE_READ_FROM_MEM(x, id)\
79 :: 1 -> CACHE_READ_FROM_MEM(x, id); \
86 CACHE_READ_FROM_MEM(alpha, get_pid());
87 CACHE_READ_FROM_MEM(beta, get_pid());
94 CACHE_WRITE_TO_MEM(alpha, get_pid());
95 CACHE_WRITE_TO_MEM(beta, get_pid());
108 * Instruction scheduling support. Declares instruction data flow dependency.
109 * INSTRUCTION_SCHED_BEGIN/INSTRUCTION_SCHED_END can be nested.
111 #define INSTRUCTION_SCHED_BEGIN(i) \
116 /* No data flow dependency between two consecutive instructions */
117 #define INSTRUCTION_SCHED_NODEP_NEXT(i) \
121 /* Has dependency between two consecutive instructions */
122 #define INSTRUCTION_SCHED_DEP_NEXT(i) \
125 #define INSTRUCTION_SCHED_END(i) \
131 RANDOM_CACHE_WRITE_TO_MEM(alpha, get_pid());
132 RANDOM_CACHE_WRITE_TO_MEM(beta, get_pid());
133 RANDOM_CACHE_READ_FROM_MEM(alpha, get_pid());
134 RANDOM_CACHE_READ_FROM_MEM(beta, get_pid());
138 /* Keep in sync manually with smp_rmb, wmp_wmb and ooo_mem */
139 DECLARE_CACHED_VAR(byte, alpha, 0);
140 DECLARE_CACHED_VAR(byte, beta, 0);
142 /* value 2 is uninitialized */
146 active proctype test_proc_one()
148 assert(get_pid() < NR_PROCS);
150 INSTRUCTION_SCHED_BEGIN();
151 WRITE_CACHED_VAR(alpha, 1);
152 INSTRUCTION_SCHED_DEP_NEXT();
154 #ifndef USE_SYNC_CORE
155 INSTRUCTION_SCHED_NODEP_NEXT();
157 // if we use a sync_core(); (equivalent to smp_mb())
158 INSTRUCTION_SCHED_DEP_NEXT();
161 INSTRUCTION_SCHED_DEP_NEXT();
162 read_one = READ_CACHED_VAR(beta);
163 INSTRUCTION_SCHED_END();
165 // test : [] (read_one == 0 -> read_two != 0)
166 // test : [] (read_two == 0 -> read_one != 0)
167 assert(!(read_one == 0 && read_two == 0));
170 active proctype test_proc_two()
172 assert(get_pid() < NR_PROCS);
174 INSTRUCTION_SCHED_BEGIN();
175 WRITE_CACHED_VAR(beta, 1);
176 INSTRUCTION_SCHED_DEP_NEXT();
178 #ifndef USE_SYNC_CORE
179 INSTRUCTION_SCHED_NODEP_NEXT();
181 // if we use a sync_core(); (equivalent to smp_mb())
182 // INSTRUCTION_SCHED_DEP_NEXT();
185 INSTRUCTION_SCHED_DEP_NEXT();
186 read_two = READ_CACHED_VAR(alpha);
187 INSTRUCTION_SCHED_END();
189 // test : [] (read_one == 0 -> read_two != 0)
190 // test : [] (read_two == 0 -> read_one != 0)
191 assert(!(read_one == 0 && read_two == 0));