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ec4e58a3 MD |
1 | #ifndef _URCU_ARCH_X86_H |
2 | #define _URCU_ARCH_X86_H | |
121a5d44 | 3 | |
6d0ce021 | 4 | /* |
af02d47e | 5 | * arch_x86.h: trivial definitions for the x86 architecture. |
6d0ce021 | 6 | * |
af02d47e MD |
7 | * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. |
8 | * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> | |
6d0ce021 | 9 | * |
af02d47e MD |
10 | * This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2.1 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
6d0ce021 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
af02d47e MD |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
18 | * Lesser General Public License for more details. | |
6d0ce021 | 19 | * |
af02d47e MD |
20 | * You should have received a copy of the GNU Lesser General Public |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA | |
6d0ce021 PM |
23 | */ |
24 | ||
ec4e58a3 | 25 | #include <urcu/compiler.h> |
121a5d44 | 26 | |
6d0ce021 PM |
27 | /* Assume P4 or newer */ |
28 | #define CONFIG_HAVE_FENCE 1 | |
29 | #define CONFIG_HAVE_MEM_COHERENCY | |
30 | ||
b4e52e3e MD |
31 | #define CACHE_LINE_SIZE 128 |
32 | ||
af02d47e | 33 | #ifndef BITS_PER_LONG |
d2d23035 | 34 | #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) |
af02d47e MD |
35 | #endif |
36 | ||
6d0ce021 PM |
37 | #ifdef CONFIG_HAVE_FENCE |
38 | #define mb() asm volatile("mfence":::"memory") | |
39 | #define rmb() asm volatile("lfence":::"memory") | |
40 | #define wmb() asm volatile("sfence"::: "memory") | |
41 | #else | |
42 | /* | |
43 | * Some non-Intel clones support out of order store. wmb() ceases to be a | |
44 | * nop for these. | |
45 | */ | |
46 | #define mb() asm volatile("lock; addl $0,0(%%esp)":::"memory") | |
47 | #define rmb() asm volatile("lock; addl $0,0(%%esp)":::"memory") | |
48 | #define wmb() asm volatile("lock; addl $0,0(%%esp)"::: "memory") | |
49 | #endif | |
50 | ||
51 | /* | |
52 | * Architectures without cache coherency need something like the following: | |
53 | * | |
54 | * #define mb() mc() | |
55 | * #define rmb() rmc() | |
56 | * #define wmb() wmc() | |
57 | * #define mc() arch_cache_flush() | |
58 | * #define rmc() arch_cache_flush_read() | |
59 | * #define wmc() arch_cache_flush_write() | |
60 | */ | |
61 | ||
62 | #define mc() barrier() | |
63 | #define rmc() barrier() | |
64 | #define wmc() barrier() | |
65 | ||
121a5d44 MD |
66 | /* Assume SMP machine, given we don't have this information */ |
67 | #define CONFIG_SMP 1 | |
68 | ||
69 | #ifdef CONFIG_SMP | |
70 | #define smp_mb() mb() | |
71 | #define smp_rmb() rmb() | |
72 | #define smp_wmb() wmb() | |
73 | #define smp_mc() mc() | |
74 | #define smp_rmc() rmc() | |
75 | #define smp_wmc() wmc() | |
76 | #else | |
77 | #define smp_mb() barrier() | |
78 | #define smp_rmb() barrier() | |
79 | #define smp_wmb() barrier() | |
80 | #define smp_mc() barrier() | |
81 | #define smp_rmc() barrier() | |
82 | #define smp_wmc() barrier() | |
83 | #endif | |
84 | ||
85 | /* Nop everywhere except on alpha. */ | |
86 | #define smp_read_barrier_depends() | |
87 | ||
92d1c656 MD |
88 | static inline void rep_nop(void) |
89 | { | |
90 | asm volatile("rep; nop" : : : "memory"); | |
91 | } | |
92 | ||
6d0ce021 PM |
93 | static inline void cpu_relax(void) |
94 | { | |
95 | rep_nop(); | |
96 | } | |
97 | ||
ebb22fff MD |
98 | /* |
99 | * Serialize core instruction execution. Also acts as a compiler barrier. | |
100 | */ | |
5dba80f9 MD |
101 | #ifdef __PIC__ |
102 | /* | |
103 | * Cannot use cpuid because it clobbers the ebx register and clashes | |
104 | * with -fPIC : | |
105 | * error: PIC register 'ebx' clobbered in 'asm' | |
106 | */ | |
107 | static inline void sync_core(void) | |
108 | { | |
109 | mb(); | |
110 | } | |
111 | #else | |
ebb22fff MD |
112 | static inline void sync_core(void) |
113 | { | |
114 | asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx"); | |
115 | } | |
5dba80f9 | 116 | #endif |
ebb22fff | 117 | |
af02d47e MD |
118 | #define rdtscll(val) \ |
119 | do { \ | |
120 | unsigned int __a, __d; \ | |
121 | asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \ | |
122 | (val) = ((unsigned long long)__a) \ | |
123 | | (((unsigned long long)__d) << 32); \ | |
124 | } while(0) | |
6d0ce021 PM |
125 | |
126 | typedef unsigned long long cycles_t; | |
127 | ||
af02d47e | 128 | static inline cycles_t get_cycles(void) |
6d0ce021 | 129 | { |
af02d47e | 130 | cycles_t ret = 0; |
6d0ce021 PM |
131 | |
132 | rdtscll(ret); | |
133 | return ret; | |
134 | } | |
121a5d44 | 135 | |
ec4e58a3 | 136 | #endif /* _URCU_ARCH_X86_H */ |