Commit | Line | Data |
---|---|---|
ec4e58a3 MD |
1 | #ifndef _URCU_ARCH_PPC_H |
2 | #define _URCU_ARCH_PPC_H | |
121a5d44 | 3 | |
6d0ce021 | 4 | /* |
af02d47e | 5 | * arch_ppc.h: trivial definitions for the powerpc architecture. |
6d0ce021 | 6 | * |
af02d47e MD |
7 | * Copyright (c) 2009 Paul E. McKenney, IBM Corporation. |
8 | * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> | |
6d0ce021 | 9 | * |
af02d47e MD |
10 | * This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2.1 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
6d0ce021 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
af02d47e MD |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
18 | * Lesser General Public License for more details. | |
6d0ce021 | 19 | * |
af02d47e MD |
20 | * You should have received a copy of the GNU Lesser General Public |
21 | * License along with this library; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA | |
6d0ce021 PM |
23 | */ |
24 | ||
ec4e58a3 | 25 | #include <urcu/compiler.h> |
c96a3726 | 26 | #include <urcu/config.h> |
121a5d44 | 27 | |
36bc70a8 MD |
28 | #ifdef __cplusplus |
29 | extern "C" { | |
30 | #endif | |
31 | ||
6d0ce021 PM |
32 | #define CONFIG_HAVE_MEM_COHERENCY |
33 | ||
b4e52e3e MD |
34 | /* Include size of POWER5+ L3 cache lines: 256 bytes */ |
35 | #define CACHE_LINE_SIZE 256 | |
36 | ||
af02d47e | 37 | #ifndef BITS_PER_LONG |
41e6b690 | 38 | #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) |
af02d47e MD |
39 | #endif |
40 | ||
6d0ce021 PM |
41 | #define mb() asm volatile("sync":::"memory") |
42 | #define rmb() asm volatile("sync":::"memory") | |
43 | #define wmb() asm volatile("sync"::: "memory") | |
44 | ||
45 | /* | |
46 | * Architectures without cache coherency need something like the following: | |
47 | * | |
48 | * #define mb() mc() | |
49 | * #define rmb() rmc() | |
50 | * #define wmb() wmc() | |
51 | * #define mc() arch_cache_flush() | |
52 | * #define rmc() arch_cache_flush_read() | |
53 | * #define wmc() arch_cache_flush_write() | |
54 | */ | |
55 | ||
56 | #define mc() barrier() | |
57 | #define rmc() barrier() | |
58 | #define wmc() barrier() | |
59 | ||
02be5561 | 60 | #ifdef CONFIG_RCU_SMP |
121a5d44 MD |
61 | #define smp_mb() mb() |
62 | #define smp_rmb() rmb() | |
63 | #define smp_wmb() wmb() | |
64 | #define smp_mc() mc() | |
65 | #define smp_rmc() rmc() | |
66 | #define smp_wmc() wmc() | |
67 | #else | |
68 | #define smp_mb() barrier() | |
69 | #define smp_rmb() barrier() | |
70 | #define smp_wmb() barrier() | |
71 | #define smp_mc() barrier() | |
72 | #define smp_rmc() barrier() | |
73 | #define smp_wmc() barrier() | |
74 | #endif | |
75 | ||
76 | /* Nop everywhere except on alpha. */ | |
77 | #define smp_read_barrier_depends() | |
78 | ||
6d0ce021 PM |
79 | static inline void cpu_relax(void) |
80 | { | |
81 | barrier(); | |
82 | } | |
83 | ||
ebb22fff MD |
84 | /* |
85 | * Serialize core instruction execution. Also acts as a compiler barrier. | |
86 | */ | |
87 | static inline void sync_core() | |
88 | { | |
89 | asm volatile("isync" : : : "memory"); | |
90 | } | |
91 | ||
af02d47e MD |
92 | #define mftbl() \ |
93 | ({ \ | |
94 | unsigned long rval; \ | |
95 | asm volatile("mftbl %0" : "=r" (rval)); \ | |
96 | rval; \ | |
97 | }) | |
98 | ||
99 | #define mftbu() \ | |
100 | ({ \ | |
101 | unsigned long rval; \ | |
102 | asm volatile("mftbu %0" : "=r" (rval)); \ | |
103 | rval; \ | |
104 | }) | |
6d0ce021 PM |
105 | |
106 | typedef unsigned long long cycles_t; | |
107 | ||
108 | static inline cycles_t get_cycles (void) | |
109 | { | |
af02d47e | 110 | long h, l; |
6d0ce021 PM |
111 | |
112 | for (;;) { | |
113 | h = mftbu(); | |
af02d47e | 114 | barrier(); |
6d0ce021 | 115 | l = mftbl(); |
af02d47e | 116 | barrier(); |
6d0ce021 | 117 | if (mftbu() == h) |
af02d47e | 118 | return (((cycles_t) h) << 32) + l; |
6d0ce021 PM |
119 | } |
120 | } | |
121a5d44 | 121 | |
36bc70a8 MD |
122 | #ifdef __cplusplus |
123 | } | |
124 | #endif | |
125 | ||
ec4e58a3 | 126 | #endif /* _URCU_ARCH_PPC_H */ |