Cleanup: move generic caa_get_cycles to arch/generic.h
[urcu.git] / urcu / arch / ppc.h
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1#ifndef _URCU_ARCH_PPC_H
2#define _URCU_ARCH_PPC_H
121a5d44 3
6d0ce021 4/*
af02d47e 5 * arch_ppc.h: trivial definitions for the powerpc architecture.
6d0ce021 6 *
af02d47e 7 * Copyright (c) 2009 Paul E. McKenney, IBM Corporation.
6982d6d7 8 * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
6d0ce021 9 *
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10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2.1 of the License, or (at your option) any later version.
05dd4b94 14 *
af02d47e 15 * This library is distributed in the hope that it will be useful,
6d0ce021 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
6d0ce021 19 *
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20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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23 */
24
ec4e58a3 25#include <urcu/compiler.h>
c96a3726 26#include <urcu/config.h>
999991c6 27#include <urcu/syscall-compat.h>
121a5d44 28
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29#ifdef __cplusplus
30extern "C" {
31#endif
32
b4e52e3e 33/* Include size of POWER5+ L3 cache lines: 256 bytes */
06f22bdb 34#define CAA_CACHE_LINE_SIZE 256
b4e52e3e 35
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36#ifdef __NO_LWSYNC__
37#define LWSYNC_OPCODE "sync\n"
38#else
39#define LWSYNC_OPCODE "lwsync\n"
40#endif
41
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42/*
43 * Use sync for all cmm_mb/rmb/wmb barriers because lwsync does not
44 * preserve ordering of cacheable vs. non-cacheable accesses, so it
45 * should not be used to order with respect to MMIO operations. An
46 * eieio+lwsync pair is also not enough for cmm_rmb, because it will
47 * order cacheable and non-cacheable memory operations separately---i.e.
48 * not the latter against the former.
49 */
e51500ed 50#define cmm_mb() __asm__ __volatile__ ("sync":::"memory")
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51
52/*
53 * lwsync orders loads in cacheable memory with respect to other loads,
54 * and stores in cacheable memory with respect to other stores.
55 * Therefore, use it for barriers ordering accesses to cacheable memory
56 * only.
57 */
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58#define cmm_smp_rmb() __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
59#define cmm_smp_wmb() __asm__ __volatile__ (LWSYNC_OPCODE:::"memory")
6d0ce021 60
af02d47e 61#define mftbl() \
1b85da85 62 __extension__ \
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63 ({ \
64 unsigned long rval; \
e51500ed 65 __asm__ __volatile__ ("mftbl %0" : "=r" (rval)); \
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66 rval; \
67 })
68
69#define mftbu() \
1b85da85 70 __extension__ \
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71 ({ \
72 unsigned long rval; \
e51500ed 73 __asm__ __volatile__ ("mftbu %0" : "=r" (rval)); \
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74 rval; \
75 })
6d0ce021 76
9a9d403a 77#define mftb() \
1b85da85 78 __extension__ \
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79 ({ \
80 unsigned long long rval; \
e51500ed 81 __asm__ __volatile__ ("mftb %0" : "=r" (rval)); \
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82 rval; \
83 })
84
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85#define HAS_CAA_GET_CYCLES
86
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87typedef unsigned long long cycles_t;
88
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89#ifdef __powerpc64__
90static inline cycles_t caa_get_cycles(void)
6d0ce021 91{
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92 return (cycles_t) mftb();
93}
94#else
95static inline cycles_t caa_get_cycles(void)
96{
97 unsigned long h, l;
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98
99 for (;;) {
100 h = mftbu();
5481ddb3 101 cmm_barrier();
6d0ce021 102 l = mftbl();
5481ddb3 103 cmm_barrier();
6d0ce021 104 if (mftbu() == h)
af02d47e 105 return (((cycles_t) h) << 32) + l;
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106 }
107}
9a9d403a 108#endif
121a5d44 109
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110/*
111 * Define the membarrier system call number if not yet available in the
112 * system headers.
113 */
114#ifndef __NR_membarrier
115#define __NR_membarrier 365
116#endif
117
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118#ifdef __cplusplus
119}
120#endif
121
1b9119f8 122#include <urcu/arch/generic.h>
e4d1eb09 123
ec4e58a3 124#endif /* _URCU_ARCH_PPC_H */
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