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1 | /* |
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> |
3 | */ |
4 | #ifndef __LTT_USERTRACE_PPC_H |
5 | #define __LTT_USERTRACE_PPC_H |
6 | |
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7 | #ifdef __powerpc64__ |
8 | #include "ltt/atomic-ppc64.h" |
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9 | #include "ltt/system-ppc64.h" |
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10 | #else |
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11 | #include "ltt/ppc_asm-ppc.h" |
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12 | #include "ltt/atomic-ppc.h" |
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13 | #include "ltt/system-ppc.h" |
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14 | #endif |
15 | |
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16 | #define CPU_FTR_601 0x00000100 |
17 | |
18 | #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ |
19 | |
20 | typedef uint64_t cycles_t; |
21 | |
22 | /* On ppc64 this gets us the whole timebase; on ppc32 just the lower half */ |
23 | static inline unsigned long get_tbl(void) |
24 | { |
25 | unsigned long tbl; |
26 | |
27 | //#if defined(CONFIG_403GCX) |
28 | // asm volatile("mfspr %0, 0x3dd" : "=r" (tbl)); |
29 | //#else |
30 | asm volatile("mftb %0" : "=r" (tbl)); |
31 | //#endif |
32 | return tbl; |
33 | } |
34 | |
35 | static inline unsigned int get_tbu(void) |
36 | { |
37 | unsigned int tbu; |
38 | |
39 | //#if defined(CONFIG_403GCX) |
40 | // asm volatile("mfspr %0, 0x3dc" : "=r" (tbu)); |
41 | //#else |
42 | asm volatile("mftbu %0" : "=r" (tbu)); |
43 | //#endif |
44 | return tbu; |
45 | } |
46 | |
47 | |
48 | #ifdef __powerpc64__ |
49 | static inline uint64_t get_tb(void) |
50 | { |
51 | return mftb(); |
52 | } |
53 | #else |
54 | static inline uint64_t get_tb(void) |
55 | { |
56 | unsigned int tbhi, tblo, tbhi2; |
57 | |
58 | do { |
59 | tbhi = get_tbu(); |
60 | tblo = get_tbl(); |
61 | tbhi2 = get_tbu(); |
62 | } while (tbhi != tbhi2); |
63 | |
64 | return ((uint64_t)tbhi << 32) | tblo; |
65 | } |
66 | #endif |
67 | |
68 | static inline cycles_t get_cycles(void) |
69 | { |
70 | return get_tb(); |
71 | } |
72 | |
73 | |
74 | #endif /* __LTT_USERTRACE_PPC_H */ |