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d3d3857f MJ |
1 | // SPDX-FileCopyrightText: 2009 Paul E. McKenney, IBM Corporation. |
2 | // SPDX-FileCopyrightText: 2009 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> | |
3 | // | |
4 | // SPDX-License-Identifier: LGPL-2.1-or-later | |
5 | ||
ec4e58a3 MD |
6 | #ifndef _URCU_ARCH_X86_H |
7 | #define _URCU_ARCH_X86_H | |
121a5d44 | 8 | |
6d0ce021 | 9 | /* |
af02d47e | 10 | * arch_x86.h: trivial definitions for the x86 architecture. |
6d0ce021 PM |
11 | */ |
12 | ||
ec4e58a3 | 13 | #include <urcu/compiler.h> |
c96a3726 | 14 | #include <urcu/config.h> |
999991c6 | 15 | #include <urcu/syscall-compat.h> |
3fa18286 | 16 | #include <stdint.h> |
121a5d44 | 17 | |
36bc70a8 MD |
18 | #ifdef __cplusplus |
19 | extern "C" { | |
67ecffc0 | 20 | #endif |
36bc70a8 | 21 | |
06f22bdb | 22 | #define CAA_CACHE_LINE_SIZE 128 |
b4e52e3e | 23 | |
0b1e236d MJ |
24 | /* |
25 | * For now, using lock; addl compatibility mode even for i686, because the | |
26 | * Pentium III is seen as a i686, but lacks mfence instruction. Only using | |
27 | * fence for x86_64. | |
28 | * | |
29 | * k1om (__MIC__) is the name for the Intel MIC family (Xeon Phi). It is an | |
30 | * x86_64 variant but lacks fence instructions. | |
31 | */ | |
32 | #if (defined(URCU_ARCH_AMD64) && !defined(URCU_ARCH_K1OM)) | |
33 | ||
34 | /* For backwards compat */ | |
35 | #define CONFIG_RCU_HAVE_FENCE 1 | |
36 | ||
e51500ed | 37 | #define cmm_mb() __asm__ __volatile__ ("mfence":::"memory") |
4e029f65 PB |
38 | |
39 | /* | |
40 | * Define cmm_rmb/cmm_wmb to "strict" barriers that may be needed when | |
41 | * using SSE or working with I/O areas. cmm_smp_rmb/cmm_smp_wmb are | |
42 | * only compiler barriers, which is enough for general use. | |
43 | */ | |
e51500ed MD |
44 | #define cmm_rmb() __asm__ __volatile__ ("lfence":::"memory") |
45 | #define cmm_wmb() __asm__ __volatile__ ("sfence"::: "memory") | |
4e029f65 PB |
46 | #define cmm_smp_rmb() cmm_barrier() |
47 | #define cmm_smp_wmb() cmm_barrier() | |
0b1e236d | 48 | |
6d0ce021 | 49 | #else |
0b1e236d | 50 | |
6d0ce021 | 51 | /* |
4e029f65 PB |
52 | * We leave smp_rmb/smp_wmb as full barriers for processors that do not have |
53 | * fence instructions. | |
54 | * | |
55 | * An empty cmm_smp_rmb() may not be enough on old PentiumPro multiprocessor | |
56 | * systems, due to an erratum. The Linux kernel says that "Even distro | |
57 | * kernels should think twice before enabling this", but for now let's | |
58 | * be conservative and leave the full barrier on 32-bit processors. Also, | |
59 | * IDT WinChip supports weak store ordering, and the kernel may enable it | |
60 | * under our feet; cmm_smp_wmb() ceases to be a nop for these processors. | |
6d0ce021 | 61 | */ |
b33e85a8 | 62 | #if (CAA_BITS_PER_LONG == 32) |
e51500ed | 63 | #define cmm_mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory") |
b33e85a8 MD |
64 | #define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory") |
65 | #define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)":::"memory") | |
66 | #else | |
67 | #define cmm_mb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory") | |
68 | #define cmm_rmb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory") | |
69 | #define cmm_wmb() __asm__ __volatile__ ("lock; addl $0,0(%%rsp)":::"memory") | |
70 | #endif | |
6d0ce021 PM |
71 | #endif |
72 | ||
2c81778b | 73 | #define caa_cpu_relax() __asm__ __volatile__ ("rep; nop" : : : "memory") |
6d0ce021 | 74 | |
f8c43f45 MD |
75 | #define HAS_CAA_GET_CYCLES |
76 | ||
af02d47e MD |
77 | #define rdtscll(val) \ |
78 | do { \ | |
79 | unsigned int __a, __d; \ | |
e51500ed | 80 | __asm__ __volatile__ ("rdtsc" : "=a" (__a), "=d" (__d)); \ |
af02d47e MD |
81 | (val) = ((unsigned long long)__a) \ |
82 | | (((unsigned long long)__d) << 32); \ | |
83 | } while(0) | |
6d0ce021 | 84 | |
3fa18286 | 85 | typedef uint64_t caa_cycles_t; |
6d0ce021 | 86 | |
3fa18286 | 87 | static inline caa_cycles_t caa_get_cycles(void) |
6d0ce021 | 88 | { |
3fa18286 | 89 | caa_cycles_t ret = 0; |
6d0ce021 PM |
90 | |
91 | rdtscll(ret); | |
92 | return ret; | |
93 | } | |
121a5d44 | 94 | |
999991c6 | 95 | /* |
84f4ccb4 MD |
96 | * On Linux, define the membarrier system call number if not yet available in |
97 | * the system headers. | |
999991c6 | 98 | */ |
84f4ccb4 | 99 | #if (defined(__linux__) && !defined(__NR_membarrier)) |
999991c6 | 100 | #if (CAA_BITS_PER_LONG == 32) |
999991c6 | 101 | #define __NR_membarrier 375 |
999991c6 | 102 | #else |
999991c6 MD |
103 | #define __NR_membarrier 324 |
104 | #endif | |
105 | #endif | |
106 | ||
67ecffc0 | 107 | #ifdef __cplusplus |
36bc70a8 MD |
108 | } |
109 | #endif | |
110 | ||
1b9119f8 | 111 | #include <urcu/arch/generic.h> |
e4d1eb09 | 112 | |
ec4e58a3 | 113 | #endif /* _URCU_ARCH_X86_H */ |